Semiconductor package

1. A semiconductor package comprising:

a semiconductor chip having a bonding pads on an upper surface thereof;

a through-electrode formed in the semiconductor chip;

a cooling part formed in the semiconductor chip and on the upper surface of the semiconductor chip; and

a redistribution line formed on the upper surface of the semiconductor chip in such a way as to electrically connect the bonding pad to the through-electrode.

2. The semiconductor package according to claim 1 , wherein the cooling part comprises:

a first cooling unit which is formed in the semiconductor chip so as to surround each of the through-electrode; and

a second cooling unit which is formed on the upper surface of the semiconductor chip.

3. The semiconductor package according to claim 2 , wherein the first cooling unit is formed to contact the through-electrode.

4. The semiconductor package according to claim 2 , wherein the first cooling unit is formed so as to surround each of the through electrode while being separated from the through-electrode so as to leave a space interposed between the first cooling unit and the through electrode.

5. The semiconductor package according to claim 2 , wherein the first cooling unit is connected to the second cooling unit.

6. A semiconductor package comprising:

at least two semiconductor chips each formed with through-electrodes therein, the at least two semiconductor chips being stacked such that the through-electrodes are electrically connected to each other;

a first cooling part formed in and on an upper surface of each of the at least two semiconductor chips, wherein the first cooling parts comprise first cooling units which are formed in the semiconductor chip so as to surround each of the through-electrodes and a second cooling unit which are formed on the upper surface of the semiconductor chip;

a substrate to be attached the stacked semiconductor chips thereto, the substrate having bond fingers which are connected to through-electrodes of a lowermost semiconductor chip of the at least two semiconductor chips; and

a second cooling part formed on an upper surface of the substrate, including the periphery of the bond finger.

7. The semiconductor package according to claim 6 , wherein the first cooling parts of the stacked semiconductor chips are connected to each other and to the second cooling part.

8. The semiconductor package according to claim 6 , further comprising:

a sealing member interposed between the first cooling parts of any two stacked semiconductor chips of the at least two semiconductor chips and interposed between the first cooling part of the lowermost semiconductor chip of the at least two semiconductor chips and the second cooling part so as to physically join the cooling parts.

9. The semiconductor package according to claim 8 , wherein the sealing members comprise polymer.

10. The semiconductor package according to claim 6 , wherein the first cooling unit is formed to contact the through-electrodes.

11. The semiconductor package according to claim 6 , wherein the first cooling unit is formed so as to surround each of the through electrode while being separated from the through-electrode so as to leave a space interposed between the first cooling unit and the through electrode.

12. The semiconductor package according to claim 6 , wherein the first cooling unit is connected to the second cooling unit.

13. The semiconductor package according to claim 6 , wherein the second cooling part includes an inlet or outlet portion which is disposed on an edge of the substrate.

14. A semiconductor package comprising:

at least two semiconductor chips each formed with through-electrodes therein, the at least two semiconductor chips being stacked such that through-electrodes are electrically connected to each other;

a first cooling part formed on an upper surface of each of the at least two semiconductor chips;

a substrate to be attached the stacked semiconductor chips thereto, the substrate having bond fingers which are connected to through-electrodes of a lowermost semiconductor chip of the at least two semiconductor chips;

a second cooling part formed on an upper surface of the substrate, including the periphery of the bond finger; and

a third cooling part disposed to contact with a side surface of the stacked semiconductor chips and connected to both the first cooling parts of the at least two semiconductor chips and the second cooling part.

15. The semiconductor package according to claim 4 , wherein the first cooling parts, the second cooling part, and the third cooling part are connected to each other.

16. The semiconductor package according to claim 14 , further comprising:

sealing members interposed between the first cooling parts and the third cooling part and between the second cooling part and the third cooling part so as to physically join the cooling parts.

17. The semiconductor package according to claim 16 , wherein the sealing members comprise polymer.

18. The semiconductor package according to claim 14 , wherein the second cooling part includes an inlet or outlet portion which is disposed on an edge of the substrate.