IP Library Granted Patent US 8,106,518
Granted Patent B2
US 8,106,518 · App. 12/640,766 · Granted Jan 31, 2012

Semiconductor device and method of manufacturing the same

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Quick Facts
Patent No.
US 8,106,518
App. No.
12/640,766
Granted
Jan 31, 2012
Kind
B2
Abstract

In a semiconductor device in which a plurality of semiconductor chips are stacked, performance is enhanced without deteriorating productivity. The semiconductor device has a plurality of elements, an interlayer insulating film, a pad, and a bump electrode electrically connected with the pad sequentially formed on a main surface of a silicon substrate and has a back-surface electrode formed on a back surface of the silicon substrate and electrically connected with the bump electrode. The bump electrode has a protruding portion penetrating through the pad and protruding toward the silicon substrate side. The back-surface electrode is formed so as to reach the protruding portion of the bump electrode from the back surface side of the silicon substrate toward the main surface side and to cover the inside of a back-surface-electrode hole portion which does not reach the pad, so that the back-surface electrode is electrically connected with the bump electrode.

Claims (72)

1. A semiconductor device comprising:

(a) a semiconductor substrate having a first main surface and a second main surface positioned on opposite sides to each other in a thickness direction of the semiconductor substrate;

(b) a plurality of elements formed on the first main surface of the semiconductor substrate;

(c) an interlayer insulating film formed on the first main surface of the semiconductor substrate so as to cover the plurality of elements;

(d) a pad formed on a surface of the interlayer insulating film so as to be electrically connected with the plurality of elements;

(e) a bump-shaped first electrode formed on the pad so as to be electrically connected with the pad; and

(f) a second electrode formed on the second main surface of the semiconductor substrate so as to be electrically connected with the first electrode, wherein

the first electrode has a protruding portion penetrating through the pad and protruding toward the semiconductor substrate side, and

the second electrode is formed so as to cover the inside of a second-electrode hole portion which reaches the protruding portion of the first electrode from the second main surface side toward the first main surface side of the semiconductor substrate and does not reach the pad so that the second electrode is electrically connected with the first electrode.

2. The semiconductor device according to claim 1 , wherein

the protruding portion of the first electrode protrudes to a depth that reaches the inside of the semiconductor substrate.

3. The semiconductor device according to claim 2 , wherein

a diameter of the protruding portion of the first electrode is smaller than a diameter of the second-electrode hole portion when the semiconductor substrate is viewed in a plan view, and

the protruding portion of the first electrode is formed so as to protrude to the inside of the second-electrode hole portion.

4. The semiconductor device according to claim 2 , wherein

a diameter of the protruding portion of the first electrode is larger than a diameter of the second-electrode hole portion when the semiconductor substrate is viewed in a plan view, and

a protective insulating film is formed at a boundary portion between the first electrode and the semiconductor substrate so that the first electrode and the semiconductor substrate are electrically insulated from each other.

5. The semiconductor device according to claim 1 , wherein

the protruding portion of the first electrode is formed so as to protrude within the interlayer insulating film without reaching the semiconductor substrate.

6. The semiconductor device according to claim 5 , wherein

a diameter of the protruding portion of the first electrode is smaller than a diameter of the second-electrode hole portion when the semiconductor substrate is viewed in a plan view.

7. The semiconductor device according to claim 5 , wherein

a diameter of the protruding portion of the first electrode is larger than a diameter of the second-electrode hole portion when the semiconductor substrate is viewed in a plan view.

8. A semiconductor device including a first chip and a second chip, each of the first chip and the second chip comprising:

(a) a semiconductor substrate having a first main surface and a second main surface positioned on opposite sides to each other in a thickness direction of the semiconductor substrate;

(b) a plurality of elements formed on the first main surface of the semiconductor substrate;

(c) an interlayer insulating film formed on the first main surface of the semiconductor substrate so as to cover the plurality of elements;

(d) a pad formed on a surface of the interlayer insulating film so as to be electrically connected with the plurality of elements;

(e) a bump-shaped first electrode formed on the pad so as to be electrically connected with the pad; and

(f) a second electrode formed on the second main surface of the semiconductor substrate so as to be electrically connected with the first electrode, wherein

the first electrode has a protruding portion penetrating through the pad and protruding toward the semiconductor substrate side,

the second electrode is formed so as to cover the inside of a second-electrode hole portion which reaches the protruding portion of the first electrode from the second main surface side toward the first main surface side of the semiconductor substrate and does not reach the pad so that the second electrode is electrically connected with the first electrode, and

the first electrode of the second chip is caulked with the second-electrode hole portion of the first chip so that the second electrode of the first chip is electrically connected with the first electrode of the second chip.

9. The semiconductor device according to claim 8 , wherein

a shape of a perimeter of the second-electrode hole portion of the first chip is circular and the first electrode of the second chip has a polygonal shape when the semiconductor substrate is viewed in a plan view.

10. The semiconductor device according to claim 8 , wherein

a shape of a perimeter of the second-electrode hole portion of the first chip is polygonal and the first electrode of the second chip is circular when the semiconductor substrate is viewed in a plan view.

11. The semiconductor device according to claim 8 , wherein,

in the second chip,

the bump-shaped first electrode has a shape in which a sidewall has an inclination at a part exposed above the pad.

12. The semiconductor device according to claim 11 , wherein,

in the second chip,

an angle formed by the sidewall of the bump-shaped first electrode and the first main surface of the semiconductor substrate is larger than or equal to 45 degrees and smaller than 70 degrees.

13. The semiconductor device according to claim 11 , wherein,

in the second chip,

an angle formed by the sidewall of the bump-shaped first electrode and the first main surface of the semiconductor substrate is larger than or equal to 70 degrees and smaller than 90 degrees.

14. A method of manufacturing a semiconductor device, comprising the steps of:

(a) sequentially forming, on a first main surface of a semiconductor substrate, a plurality of elements, an interlayer insulating film covering the plurality of elements, and a pad disposed on a surface of the interlayer insulating film and electrically connected with the plurality of elements;

(b) forming a first-electrode hole portion on the surface of the interlayer insulating film so that the first-electrode hole portion penetrates through the pad and has a depth toward the semiconductor substrate side;

(c) forming a bump-shaped first electrode so as to fill the first-electrode hole portion and be electrically connected with the pad;

(d) forming a second-electrode hole portion from a second main surface, which is positioned on the opposite side of the first main surface of the semiconductor substrate in a thickness direction of the semiconductor substrate, toward the first main surface side so as to reach the first-electrode hole portion and not reach the pad; and

(e) forming a second electrode so as to cover the inside of the second-electrode hole portion and be electrically connected with the first electrode, wherein

the first electrode having a protruding portion penetrating through the pad and protruding toward the semiconductor substrate side is formed through the steps (b) and (c).

15. The method of manufacturing a semiconductor device according to claim 14 , further comprising a step of,

after the step (b) and before the step (c),

(f) forming a first-electrode seed layer so as to cover the interlayer insulating film including an inner wall of the first-electrode hole portion, wherein,

in the step (c), the first electrode is formed by an electrolytic plating method.

16. The method of manufacturing a semiconductor device according to claim 15 , further comprising a step of,

after the step (c) and before the step (d),

(g) removing part of the first-electrode seed layer, the part not being covered with the first electrode.

17. The method of manufacturing a semiconductor device according to claim 16 , wherein,

in the step (b), the first-electrode hole portion is formed to a depth to penetrate through the interlayer insulating film and reach the semiconductor substrate.

18. The method of manufacturing a semiconductor device according to claim 17 , wherein,

in the step (d), when viewed in a plan view, the second-electrode hole portion is formed to have a diameter larger than a diameter of the protruding portion of the first electrode formed in the steps (b) and (c), and

the protruding portion of the first electrode is formed to protrude to the inside, of the second-electrode hole portion.

19. The method of manufacturing a semiconductor device according to claim 17 , further comprising a step of,

after the step (b) and before the step (c),

(h) forming a protective insulating film so as to cover the inner wall of the first-electrode hole portion, wherein,

in the step (d), when viewed in a plan view, a diameter of the second-electrode hole portion is formed to be smaller than a diameter of the protruding portion of the first electrode formed in the steps (b), (c), and (h); and

the first electrode and the semiconductor substrate are electrically insulated from each other by forming the protective insulating film at a boundary part between the first electrode and the semiconductor substrate.

20. The method of manufacturing a semiconductor device according to claim 16 , wherein,

in the step (b), the first-electrode hole portion is formed to a depth within the interlayer insulating film without penetrating through the interlayer insulating film.

Assignments (8)
CHANGE OF NAME Recorded Nov 19, 2025
From: TESSERA ADVANCED TECHNOLOGIES, INC.
To: ADEIA SEMICONDUCTOR ADVANCED TECHNOLOGIES INC.
Reel/Frame 073635/0304 →
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION; TESSERA ADVANCED TECHNOLOGIES, INC; DTS, INC.; DTS LLC; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 052920/0001 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
SECURITY INTEREST Recorded Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.; DIGITALOPTICS CORPORATION; DIGITALOPTICS CORPORATION MEMS; DTS, LLC; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 13, 2014
From: RENESAS ELECTRONICS CORPORATION
To: TESSERA ADVANCED TECHNOLOGIES, INC.
Reel/Frame 032892/0212 →
CHANGE OF NAME Recorded Sep 15, 2010
From: NEC ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 024988/0161 →
MERGER Recorded Sep 15, 2010
From: RENESAS TECHNOLOGY CORP.
To: NEC ELECTRONICS CORPORATION
Reel/Frame 024987/0833 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 23, 2010
From: KAWASHITA, MICHIHIRO; YOSHIMURA, YASUHIRO; TANAKA, NAOTAKA; NAITO, TAKAHIRO; AKAZAWA, TAKASHI
To: RENESAS TECHNOLOGY CORP.
Reel/Frame 023977/0058 →