Clock receiver in semiconductor integrated circuit and method of controlling the same

1. A clock receiver in a semiconductor integrated circuit comprising:

a first clock buffer configured to buffer an input clock to generate a first buffered clock in response to a first operation signal, wherein the first buffered clock has a substantially same frequency with the input clock;

a second clock buffer configured to buffer the input clock to generate a second buffered clock in response to a second operation signal, wherein the second buffered clock has a substantially same frequency with the input clock; and

an internal clock generating unit configured to receive the first buffered clock and the second buffered clock, to disable one of the first operation signal and the second operation signal and to generate an internal clock,

wherein a frequency of the input clock has a substantially same with a frequency of the internal clock.

2. The clock receiver of claim 1 , wherein the first clock buffer is configured to be activated in a first frequency region and to be deactivated in a second frequency region to output a signal having a logic low level.

3. The clock receiver of claim 2 , wherein the first clock buffer includes:

a first buffering unit configured to buffer the input clock to output a first clock pair in response to the first operation signal and a first bias voltage;

a second buffering unit configured to buffer the first clock pair to output a second clock in response to the first operation signal and a second bias voltage; and

a first driving unit configured to drive the second clock to generate the first buffered clock.

4. The clock receiver of claim 3 , wherein the second clock buffer includes:

a third buffering unit configured to buffer the input clock to output a third clock pair in response to the second operation signal and a third bias voltage;

a fourth buffering unit configured to buffer the third clock pair to output a fourth clock in response to the second operation signal and a fourth bias voltage; and

a second driving unit configured to drive the fourth clock to generate the high frequency buffered clock; and

wherein the level of the third bias voltage is configured to be higher than the level of the first bias voltage, and the level of the fourth bias voltage is configured to be higher than the level of the second bias voltage.

5. The clock receiver of claim 1 , wherein the clock generating unit is configured to enable both the first operation signal and the second operation signal at the beginning of the operation.

6. The clock receiver of claim 5 , wherein when the first buffered clock is disabled, the clock generating unit is configured to disable the first operation signal, to substantially maintain an enable state of the second operation signal and to drive the second buffered clock to generate the internal clock.

7. The clock receiver of claim 6 , wherein when the first buffered clock is enabled, the clock generating unit is configured to disable the second operation signal, to substantially maintain an enable state of the first operation signal and to drive the first buffered clock to generate the internal clock.

8. The clock receiver of claim 7 , wherein the clock generating unit includes:

a first detection unit configured to detect whether or not the first buffered clock is enabled to generate a first detection signal;

a second detection unit configured to detect whether or not the second buffered clock is enabled to generate a second detection signal;

a buffer control unit configured to generate a third detection signal in response to the first detection signal and the second detection signal, and to generate the first operation signal and the second operation signal in response to the first detection signal and the third detection signal; and

a driving unit configured to drive either the first buffered clock or the second buffered clock to generate the internal clock, in response to the first detection signal and the third detection signal.

9. A method of controlling a clock receiver in a semiconductor integrated circuit comprising:

enabling a first operation signal and a second operation signal to activate a first clock buffer and a second clock buffer;

detecting whether or not a first buffered clock is generated from the first clock buffer;

disabling either the first operation signal or the second operation signal; and

outputting either the first buffered clock or a second buffered clock generated from the second clock buffer, as an internal clock,

wherein the first buffered clock or the second buffered clock has a same frequency with the input clock.

10. The method of claim 9 , wherein detecting whether or not the first buffered clock is generated and disabling either the first operation signal or the second operation signal includes disabling the second operation signal and substantially maintaining an enable state of the first operation signal, when the first buffered clock toggles is detected.

11. The method of claim 10 , wherein outputting the internal clock includes driving the first buffered clock to generate the internal clock.

12. The method of claim 9 , wherein detecting whether or not the first buffered clock is generated and disabling either the first operation signal or the second operation signal includes disabling the first operation signal and substantially maintaining an enable state of the second operation signal, when the first buffered clock is disabled is detected.

13. The method of claim 12 , wherein outputting the internal clock includes driving the second buffered clock to generate the internal clock.

14. The method of claim 9 , wherein the second clock buffer is provided with a bias voltage higher than a bias voltage provided to the first clock buffer.