Self-refresh test circuit of semiconductor memory apparatus
View Patent ↗A self-refresh test circuit includes a test clock generation unit, a pulse generation unit, a period signal selection unit, and a self-refresh pulse control unit. The test clock generation unit divides a clock signal to generate a plurality of divided clock signals having different periods when a test enable signal is enabled, and outputs one of the plurality of divided clock signals as a selected clock signal. The pulse generation unit generates a test period signal in response to the selected clock signal. The period signal selection unit outputs one of the test period signal and a self-refresh period signal as a selected period signal. The self-refresh pulse control unit generates a self-refresh pulse in response to a self-refresh exit signal and the selected period signal.
1. A self-refresh test circuit comprising:
a test clock generation unit configured to divide a clock signal to generate a plurality of divided clock signals having different periods when a test enable signal is enabled, and to output one of the plurality of divided clock signals as a selected clock signal;
a pulse generation unit configured to generate a test period signal in response to the selected clock signal;
a period signal selection unit configured to output one of the test period signal and a self-refresh period signal as a selected period signal; and
a self-refresh pulse control unit configured to generate a self-refresh pulse in response to a self-refresh exit signal and the selected period signal.
2. The self-refresh test circuit according to claim 1 , wherein the test clock generation unit comprises:
a divided clock generation section configured to divide the clock signal to generate the plurality of divided clock signals when the test enable signal is enabled; and
a divided clock selection section configured to output one of the plurality of divided clocks as the selected clock signal in response to a test selection signal.
3. The self-refresh test circuit according to claim 2 , wherein the divided clock generation section comprises a plurality of dividers connected in series.
4. The self-refresh test circuit according to claim 1 , wherein the pulse generation unit generates a pulse which is enabled whenever the selected clock signal transits at a specific level, and outputs the generated pulse as the test period signal.
5. The self-refresh test circuit according to claim 1 , wherein the pulse generation unit generates a pulse which is enabled whenever the selected clock signal rises, and outputs the generated pulse as the test period signal.
6. The self-refresh test circuit according to claim 1 , wherein the period signal selection unit outputs the self-refresh period signal as the selected period signal when the test period signal is disabled, and outputs the test period signal as the selected period signal when the self-refresh period signal is disabled.
7. The self-refresh test circuit according to claim 1 , wherein the self-refresh pulse control unit outputs the selected period signal as the self-refresh pulse when the self-refresh exit signal is disabled, and fixes the self-refresh pulse at a specific level when the self-refresh exit signal is enabled.
8. A self-refresh test circuit comprising:
a test period signal generation unit configured to generate a pulse which is enabled every predetermined period in response to a test enable signal and to output the generated pulse as a test period signal;
a period signal selection unit configured to output a self-refresh period signal or the test period signal as a selected period signal; and
a self-refresh pulse control unit configured to generate a self-refresh pulse in response to a self-refresh exit signal and the selected period signal,
wherein the period signal selection unit is configured to output the self-refresh period signal as the selected period signal when the test period signal is disabled, and to output the test period signal as the selected period signal when the self-refresh period signal is disabled.
9. The self-refresh test circuit according to claim 8 , wherein the test period signal generation unit comprises
a divided clock generation section configured to divide a clock signal when the test enable signal is enabled, and to generate a plurality of divided clock signals having different periods;
a divided clock selection section configured to select one of the plurality of divided clock signals in response to a test selection signal, and to output the divided clock signal selected by the test selection signal as a selected clock signal; and
a pulse generation section configured to generate the pulse whenever the selected clock rises, and to output the generated pulse as the test period signal.
10. The self-refresh test circuit according to claim 8 , wherein the self-refresh pulse control unit is configured to output the selected period signal as the self-refresh pulse when the self-refresh exit signal is disabled, and configured to fix the self-refresh pulse at a specific level when the self-refresh exit signal is enabled.