System and method for metal-oxide-semiconductor field effect transistor

1. A field effect transistor (FET), the FET comprising:

a substrate material, the substrate material being characterized by a first conductivity type, the substrate material including a first portion, a second portion, and a third portion, the third portion being positioned between the first portion and the second portion;

a source portion positioned within the first portion, the source portion being characterized by a second conductivity type, the second conductivity type being opposite of the first conductivity type;

a first drain portion positioned within the second portion, the first drain portion being characterized by the second conductivity type and a first doping concentration;

a second drain portion positioned within the second portion, the second drain portion being characterized by the second conductivity type and a second doping concentration, the second doping concentration being different from the first doping concentration;

a first dielectric material, the first dielectric material overlaying all of the third portion, the first dielectric material partially overlaying the source portion, the first dielectric material partially overlaying the first and the second drain portions; and

a conducting material overlaying the first dielectric material, the conducting material being configured to provide a gate contact;

wherein the first and second drain portions share a boundary with the third portion,

wherein the first and second drain portions are disposed side by side.

2. The FET of claim 1 wherein the first drain portion is characterized by a higher doping concentration than the second drain portion.

3. The FET of claim 1 wherein each of the source portion and the first drain portion comprises lightly-doped drain dopants and heavily doped drain dopants, and the second drain portion is free from the heavily doped drain dopants.

4. The FET of claim 3 wherein the heavily doped drain dopants are blocked from the second drain portion with a silicide blocking layer.

5. The FET of claim 1 wherein the first drain portion comprises a first region and a second region disposed on either side of the second drain portion.

6. The FET of claim 1 wherein the second drain portion is configured to receive a bias voltage to modify a current flow between the source portion and the first drain portion.

7. The FET of claim 1 wherein the second drain portion is configured to receive a bias voltage to modify a subthreshold current flow between the source portion and the first drain portion.

8. The FET of claim 1 wherein the first conductivity type is p-type.

9. The FET of claim 1 further comprising:

a first layer overlaying the source portion;

a second layer overlaying the first drain portion, the second layer including a first material;

a third layer overlaying the second drain portion, the third layer including a second material, the second material being different from the first material.

10. The FET of claim 9 wherein:

the first material is a silicide material;

the second material is a silicide blocking layer material.

11. The FET of claim 1 further comprising:

a first drain contact overlaying the first drain portion;

a second drain contact overlaying the second drain portion, the second drain contact being located away from the first drain contact at a first distance.

12. The FET of claim 11 wherein the first drain contact is electrically coupled to a first voltage supply and the second drain contact is electrically coupled to a second voltage supply.

13. A field effect transistor (FET), the FET comprising:

a substrate material, the substrate material being characterized by a first conductivity type, the substrate material including a first portion, a second portion, and a third portion, the third portion being positioned between the first portion and the second portion;

a source portion positioned within the first portion, the source portion being characterized by a second conductivity type, the second conductivity type being opposite of the first conductivity type;

a first drain portion positioned within the second portion, the first drain portion being characterized by the second conductivity type and a first doping concentration;

a second drain portion positioned within the second portion, the second drain portion being characterized by the second conductivity type and a second doping concentration, the second drain portion comprises a different material from the first drain portion;

a first dielectric material, the first dielectric material overlaying all of the third portion, the first dielectric material partially overlaying the source portion, the first dielectric material partially overlaying the first and the second drain portions; and

a conducting material overlaying the first dielectric material, the conducting material being configured to provide a gate contact;

wherein the first and second drain portions share a boundary with the third portion,

wherein the first and second drain portions are disposed side by side.

14. The FET of claim 13 wherein the first drain portion comprises a region that is doped with a p+ material, the first drain portion being covered by a cobald salicide layer.

15. The FET of claim 13 wherein the second drain portion comprises a region that is free of p+ dopants, the second drain region being covered by a salicide blocking layer.

16. The FET of claim 13 further comprising:

a first drain contact overlaying the first drain portion;

a second drain contact overlaying the second drain portion, the second drain contact being located away from the first drain contact at a distance.

17. The FET of claim 16 wherein the first drain contact is electrically coupled to a first voltage supply and the second drain contact is electrically coupled to a second voltage supply.

18. A field effect transistor (FET), the FET comprising:

a substrate material, the substrate material being characterized by a first conductivity type, the substrate material including a first portion, a second portion, and a third portion, the third portion being positioned between the first portion and the second portion;

a drain portion positioned within the first portion, the drain portion being characterized by a second conductivity type, the second conductivity type being opposite of the first conductivity type;

a first source portion positioned within the second portion, the first source portion being characterized by the second conductivity type and a first doping concentration;

a second source portion positioned within the second portion, the second source portion being different from the first source portion, the second source portion being characterized by the second conductivity type and a second doping concentration;

a first dielectric material, the first dielectric material overlaying all of the third portion, the first dielectric material partially overlaying the first and the second source portions, the first dielectric material partially overlaying the drain portion; and

a conducting material overlaying the first dielectric material, the conducting material being configured to provide a gate contact;

wherein the first and second source portions share a boundary with the third portion,

wherein the first and second source portions are disposed side by side.

19. The FET of claim 18 wherein:

the first source portion comprises p+ implants,

the second source portion is free from p+ implants,

the first conductivity type is n-type.

20. The FET of claim 18 wherein the first conductivity is p-type.