Semiconductor memory, memory system, and method of controlling the same
View Patent ↗Various embodiments of a semiconductor system, a semiconductor memory, and a method of controlling the same are disclosed. In one exemplary embodiment, the semiconductor memory may include a first circuit area configured to perform an operation corresponding to a general operation command and a second circuit area configured to provide the general operation command to the first circuit area. The second circuit area may be configured to determine whether the semiconductor memory is selected to perform the operation based on unique identification information and target identification information allocated to the semiconductor memory.
1. A memory system comprising:
a memory controller configured to generate an identification information store command, an identification information check command, a general operation command, an unique identification information, and a target identification information; and
a plurality of semiconductor memories configured to store the unique identification information in response to the identification information store command and to select one or more of the plurality of semiconductor memories simultaneously based on the target identification information and the unique identification information in response to the identification information check command,
wherein, the selected one or more of the plurality of semiconductor memories are configured to perform an operation corresponding to the general operation command,
wherein each semiconductor memory of the plurality of semiconductor memories comprises:
a first circuit area configured to perform the operation corresponding to the general operation command; and
a second circuit area configured to store the unique identification information and provide the general operation command to the first circuit area depending on whether or not the semiconductor memory is selected.
2. The memory system according to claim 1 , wherein the memory controller is configured to provide the identification information store command and the unique identification information at an initialization interval of the memory system.
3. The semiconductor memory according to claim 1 , wherein the first circuit area comprises a peripheral circuit and memory area.
4. The semiconductor memory according to claim 1 , wherein the second circuit area is configured to receive the unique identification information through a data channel and receive the target identification information through an address channel.
5. The semiconductor memory according to claim 1 , wherein the second circuit area comprises:
a command decoder configured to generate a first strobe signal in response to the identification information store command, generate a second strobe signal in response to the identification information check command, and decode the general operation command;
a first storage unit configured to store the unique identification information in response to the first strobe signal;
a second storage unit configured to store the target identification information in response to the second strobe signal;
an identification information determination unit configured to select one bit of the target identification information in accordance with the unique identification information, and output the selected bit as an identification information confirm signal; and
a command transfer control unit configured to provide the general operation command to the first circuit area in response to the identification information confirm signal.
6. A method of controlling a memory system comprising a plurality of semiconductor memories, the method comprising:
generating an identification information store command and allocating unique identification information to the plurality of semiconductor memories;
generating an identification information check command to select one or more of the plurality of semiconductor memories simultaneously; and
generating a general operation command and providing the general operation command in common to the plurality of semiconductor memories, after generating the identification information check command,
wherein each semiconductor memory of the plurality of semiconductor memories comprises:
a first circuit area configured to perform the operation corresponding to the general operation command; and
a second circuit area configured to store the unique identification information and provide the general operation command to the first circuit area depending on whether or not the semiconductor memory is selected.
7. The method according to claim 6 , wherein allocating the unique identification information comprises transferring the unique identification information to the plurality of semiconductor memories through data channels which are individually connected to the respective semiconductor memories.
8. The method according to claim 6 , wherein selecting one or more of the semiconductor memories comprises:
transferring target identification information to the plurality of semiconductor memories through an address channel connected in common to the plurality of semiconductor memories; and
at each of the semiconductor memories, checking whether or not the unique identification information is designated in the target identification information.
9. A memory system comprising:
a plurality of semiconductor memories configured to be allocated unique identification information and, wherein the selected one or more of the plurality of semiconductor memories are configured to perform an operation in response to a general operation command,
wherein each semiconductor memory of the plurality of semiconductor memory comprises:
a first circuit area configured to perform the operation corresponding to the general operation command; and
a second circuit area configured to store the unique identification information and provide the general operation command to the first circuit area depending on whether or not the semiconductor memory is selected; and
a memory controller configured to allocate the unique identification information to the plurality of semiconductor memories, to select the one or more of the plurality of semiconductor memories simultaneously, and to supply the general operation command to the plurality of semiconductor memories.
10. The memory system according to claim 9 , wherein the memory controller is configured to provide the unique identification information at an initialization interval of the memory system.
11. The semiconductor memory according to claim 9 , wherein the first circuit area comprises a peripheral circuit and memory area.
12. The semiconductor memory according to claim 9 , wherein the second circuit area is configured to receive the unique identification information through a data channel.
13. The semiconductor memory according to claim 9 , wherein the second circuit area comprises:
a command decoder configured to generate a first strobe signal in response to an identification information store command from the memory controller, generate a second strobe signal in response to an identification information check command from the memory controller, and decode the general operation command;
a first storage unit configured to store the unique identification information in response to the first strobe signal;
a second storage unit configured to store a target identification information from the memory controller in response to the second strobe signal;
an identification information determination unit configured to select one bit of the target identification information in accordance with the unique identification information, and output the selected bit as an identification information confirm signal; and
a command transfer control unit configured to provide the general operation command to the first circuit area in response to the identification information confirm signal.