Three-dimensional semiconductor devices including select gate patterns having different work function from cell gate patterns
View Patent ↗A three-dimensional semiconductor device includes a vertical channel pattern on the substrate, a plurality of cell gate patterns and a select gate pattern stacked on the substrate along the sidewall of the vertical channel pattern, a charge storage pattern between the vertical channel pattern and the cell gate pattern and a select gate pattern between the vertical channel pattern and the select gate pattern. The select gate pattern has a different work function from the cell gate pattern.
1. A three-dimensional semiconductor device comprising:
a substrate;
a vertical channel pattern on the substrate;
a plurality of cell gate patterns and a select gate pattern stacked on the substrate along a sidewall of the vertical channel pattern;
a charge storage pattern between the vertical channel pattern and the cell gate patterns;
a ground select gate pattern between the substrate and a lowermost pattern among the cell gate patterns; and
a select gate pattern insulating layer between the vertical channel pattern and the select gate pattern,
wherein the select gate pattern has a different work function from the cell gate patterns, and
wherein the select gate pattern is stacked on an uppermost pattern among the cell gate patterns and extends in a first direction.
2. The three-dimensional semiconductor device of claim 1 , wherein the work function of the select gate pattern is greater than that of the cell gate pattern when charges stored in the charge storage pattern during a program operation are electrons.
3. The three-dimensional semiconductor device of claim 1 , wherein the cell gate pattern and the select gate pattern include semiconductors doped with dopants of different conductivity types respectively.
4. The three-dimensional semiconductor device of claim 3 , wherein the cell gate pattern includes N-type dopants and the select gate pattern includes P-type dopants when charges stored in the charge storage pattern during a program operation are electrons.
5. The three-dimensional semiconductor device of claim 1 , wherein the charge storage pattern includes a blocking insulating layer adjacent to the cell gate patterns, a tunnel insulating layer adjacent to the vertical channel pattern, and a charge storage layer between the blocking insulating layer and the tunnel insulating layer.
6. The three-dimensional semiconductor device of claim 1 , further comprising:
a bitline disposed over the select gate pattern and extending in a second direction which is perpendicular to the first direction.
7. The three-dimensional semiconductor device of claim 1 , wherein the charge storage pattern and the select gate insulating layer contain the same material.
8. The three-dimensional semiconductor device of claim 1 , further comprising:
insulating layers sandwiched between the cell gate patterns and the select gate pattern, respectively.
9. A three-dimensional semiconductor device comprising:
a substrate;
a vertical channel pattern on the substrate;
a plurality of cell gate patterns and a select gate pattern stacked on the substrate along a sidewall of the vertical channel pattern;
a charge storage pattern between the vertical channel pattern and the cell gate patterns; and
a ground select gate pattern between the substrate and a lowermost pattern among the cell gate patterns, wherein the ground select gate pattern has a different work function from at least one of the cell gate patterns,
wherein the select gate pattern has a different work function from at least one of the cell gate patterns, and
wherein the select gate pattern is a string select gate pattern that is stacked on an uppermost pattern among the cell gate patterns.
10. The three-dimensional semiconductor device of claim 9 , wherein the work function of the string select gate pattern is greater than that of the at least one cell gate pattern when charges stored in the charge storage pattern during a program operation are electrons.
11. The three-dimensional semiconductor device of claim 9 , wherein the at least one cell gate pattern and the string select gate pattern include semiconductors doped with dopants of different conductivity types respectively.
12. The three-dimensional semiconductor device of claim 11 , wherein the at least one cell gate pattern includes N-type dopants and the string select gate pattern includes P-type dopants when charges stored in the charge storage pattern during a program operation are electrons.
13. The three-dimensional semiconductor device of claim 9 , wherein the charge storage pattern includes a blocking insulating layer adjacent to the cell gate patterns, a tunnel insulating layer adjacent to the vertical channel patterns, and a charge storage layer between the blocking insulating layer and the tunnel insulating layer.
14. The three-dimensional semiconductor device of claim 9 , further comprising:
a bitline disposed over the string select gate pattern.
15. The three-dimensional semiconductor device of claim 9 , wherein the charge storage pattern and the select gate insulating layer contain the same material.
16. The three-dimensional semiconductor device of claim 9 , wherein the string select gate pattern and the ground select gate pattern both have work functions that are different from all of the cell gate patterns.