Processor system and operation mode switching method for processor system

1. A processor system comprising:

a first processor comprising a first combinational circuit and a first memory circuit that temporarily stores an output value of the first combinational circuit and supplies an input value to the first combinational circuit, the first processor being configured to perform processing in response to a supplied instruction stream;

a second processor comprising a second combinational circuit and a second memory circuit that temporarily stores an output value of the second combinational circuit and supplies an input value to the second combinational circuit, the second processor being configured to perform processing in response to a supplied instruction stream;

a control unit that switches an operation mode between a lock step mode for the first and second processors to execute a same instruction stream and a free step mode for the first and second processors to execute different instruction streams;

a signal line group that includes at least one signal line disposed between the first memory circuit and the second memory circuit and is capable of transferring a storage state of the first memory circuit to the second memory circuit; and

a selection circuit capable of switching a connection destination of the second memory circuit between the second combinational circuit and the signal line group.

2. The processor system according to claim 1 , wherein

the selection circuit operates in accordance with a control by the control unit,

the selection circuit is controlled to connect the second memory circuit to the signal line group during a first stop period for stopping an execution of instruction streams by the first and second processors so as to switch from the free step mode to the lock step mode, and

the selection circuit is controlled to connect the second memory circuit to the second combinational circuit during the execution of instruction streams by the first and second processors.

3. The processor system according to claim 1 , wherein

the signal line group and the selection circuit are configured to connect a first part of a first plurality of memory elements included in the first memory circuit and a first part of a second plurality of memory elements included in the second memory circuit, and

at least a part of a second part of the first plurality of memory elements and at least a part of a second part of the second plurality of memory elements are updated with a predetermined fixed value during a first stop period.

4. The processor system according to claim 3 , wherein each of the first and second processors further comprises a fixed value generation circuit that generates the predetermined fixed value.

5. The processor system according to claim 1 , wherein

each of the first and second processors further comprises a start address holding circuit capable of holding a start address for use in starting the free step mode,

the control unit supplies different start addresses to the start address holding circuits of the first and second processors during a second stop period for stopping execution of instruction streams by the first and second processors so as to switch from the lock step mode to the free step mode, and

the first and second processors are configured to fetch the start addresses held in the start address holding circuits of the first and second processors and resume execution, upon returning from the second stop period.

6. The processor system according to claim 1 , wherein

the control unit is configured to send a stop request to each of the first and second processors when the operation mode is switched,

the first and second processors are configured to stop execution of instruction streams in response to the stop request and to send a stop completion response to the control unit, and

the control unit stops a clock supply to the first and second processors on a condition of receiving the stop completion response from the first and second processors.

7. The processor system according to claim 6 , wherein processing executed by the first and second processors in response to the stop request comprises:

stopping an acquisition of a new instruction;

processing any instructions residing in the processors; and

sending the stop completion response upon completion of any instructions residing in the processors.

8. The processor system according to claim 1 , wherein each of the first and second memory circuits includes at least one of a program counter, a program status word (PSW) register, and a pipeline register.

9. The processor system according to claim 1 , wherein at least a part of a first plurality of memory elements included in the first memory circuit and at least a part of a second plurality of memory elements included in the second memory circuit are updated by a predetermined fixed value during the first stop period.

10. The processor system according to claim 1 , wherein each of the first and second processors further comprises a start address holding circuit capable of holding a start address for use in starting the free step mode, and

the control unit supplies different start addresses to the start address holding circuits of the first and second processors during a second stop period for stopping execution of instruction streams by the first and second processors so as to switch from the lock step mode to the free step mode.

11. The processor system according to claim 1 , wherein the control unit stops a clock supply to the first and second processors on a condition of receiving a stop completion response from the first and second processors.

12. The processor system according to claim 1 , wherein the storage state of the first memory circuit includes at least one of an internal state of the first processor and an execution state of the first processor.

13. A processor system comprising:

a first processor and a second processor that are configured to be capable of switching an operation mode between a lock step mode for the first and second processors to execute a same instruction stream and a free step mode for the first and second processors to execute different instruction streams; and

a hardware circuit that is disposed between a first memory circuit included in the first processor and a second memory circuit included in the second processor, and said hardware circuit selectively connects the first and second memory circuits during a stop period for stopping execution of instruction streams by the first and second processors so as to switch from the free step mode to the lock step mode.

14. The processor system according to claim 13 , wherein

the hardware circuit is configured to connect a first part of a first plurality of memory elements included in the first memory circuit and a first part of a second plurality of memory elements included in the second memory circuit, and

at least a part of a second part of the first plurality of memory elements and at least a part of a second part of the second plurality of memory elements are updated with a predetermined fixed value during the stop period.

15. The processor system according to claim 14 , wherein each of the first and second processors further comprises a fixed value generation circuit that generates the fixed value.

16. The processor system according to claim 13 , wherein,

the first memory circuit is configured to store at least one of an internal state of the first processor and an execution state of the first processor, and

the hardware circuit is configured to transfer the at least one of the internal state and the execution state stored in the first memory circuit to the second memory circuit.

17. An operation mode switching method for a processor system including a first processor and a second processor,

the processor system being configured to be capable of switching an operation mode between a lock step mode for the first and second processors to execute a same instruction stream and a free step mode for the first and second processors to execute different instruction streams,

the first processor comprising a first combinational circuit and a first memory circuit that temporarily stores an output value of the first combinational circuit and supplies an input value to the first combinational circuit,

the second processor comprising a second combinational circuit and a second memory circuit that temporarily stores an output value of the second combinational circuit and supplies an input value to the second combinational circuit,

the operation mode switching method comprising:

transferring a storage state of the first memory circuit to the second memory circuit during a first stop period for stopping execution of instruction streams by the first and second processors so as to switch from the free step mode to the lock step mode, by controlling a selection circuit disposed between the first memory circuit and the second memory circuit.

18. The operation mode switching method according to claim 17 , wherein

each of the first and second processors further comprises a start address holding circuit capable of holding a start address for use in starting the free step mode, and

the operation mode switching method further comprises:

supplying different start addresses to the start address holding circuits of the first and second processors during a second stop period for stopping execution of instruction streams by the first and second processors so as to switch from the lock step mode to the free step mode; and

fetching, by the first and second processors, the start addresses held in the start address holding circuits of the first and second processors and resuming execution, upon returning from the second stop period.

19. The operation mode switching method according to claim 17 , further comprising:

sending a stop request to each of the first and second processors when the operation mode is switched;

stopping execution of instruction streams by the first and second processors in response to the stop request, and sending a stop completion response to the control unit; and

stopping a clock supply to the first and second processors on condition of receiving the stop completion response from the first and second processors.

20. The operation mode switching method according to claim 19 , wherein processing executed by the first and second processors in response to the stop request comprises:

stopping an acquisition of a new instruction;

processing any instructions residing in the processors; and

sending the stop completion response upon completion of any instructions residing in the Processors.