Comparator circuit

1. A comparator circuit, comprising:

first and second terminals, a reference voltage that determines a threshold voltage being inputted between the first and second terminals;

a third terminal to which a standard voltage is inputted;

a fourth terminal to which a target voltage that is to be detected and is based on the standard voltage is inputted;

first and second transistors of a first conductivity type including control terminals connected to the first and second terminals, respectively, the first and second transistors flowing currents depending on a potential difference of the reference voltage;

a third transistor of a second conductivity type connected between the first transistor and the fourth terminal; and

a fourth transistor of the second conductivity type connected between the second transistor and the third terminal, the fourth transistor flowing a mirror current depending on a current passing through the third transistor,

wherein a voltage depending on a voltage of an intermediate node between the second and fourth transistors is outputted as an output signal that includes a comparison result between the reference voltage and a voltage difference between the target voltage and the standard voltage.

2. The comparator circuit according to claim 1 , wherein:

the third and fourth transistors comprises MOS transistors each having a high breakdown voltage;

a drain of the first transistor is connected to a drain of the third transistor; and

a drain of the second transistor is connected to a drain of the fourth transistor.

3. The comparator circuit according to claim 1 , wherein the third transistor comprises an MOS transistor, and

wherein a substrate terminal of the third transistor is connected to the third terminal.

4. The comparator circuit according to claim 1 wherein:

the first and second transistors have a same configuration; and

the third and fourth transistors have a same configuration.

5. The comparator circuit according to claim 1 , wherein:

the first and third transistors are connected in series between a fifth terminal and the fourth terminal;

the second and fourth transistors are connected in series between the fifth terminal and the third terminal; and

an operating voltage of the comparator circuit is applied across the third and fifth terminals.

6. The comparator circuit according to claim 5 , wherein the standard voltage inputted to a source of the fourth transistor is a ground voltage.

7. The comparator circuit according to claim 5 , wherein the standard voltage inputted to a source of the fourth transistor is a power supply voltage.

8. The comparator circuit according to claim 1 , further comprising at least one inverter circuit that buffers the voltage of the intermediate node between the second and fourth transistors.

9. The comparator circuit according to claim 4 , wherein the first and second transistors have a same size, and

wherein the third and fourth transistors have a same size.

10. The comparator circuit according to claim 1 , wherein a drain of the first transistor is coupled to a drain of the third transistor such that a current passing through the first transistor passes through the third transistor.

11. The comparator circuit according to claim 1 , wherein different potentials are applied to the control terminals of the first and second transistors.

12. The comparator circuit according to claim 1 , wherein the reference voltage is independent of a threshold voltage of the third transistor.

13. A method of operating a comparator, the comparator comprising:

a first power source terminal;

a second power source terminal;

a first transistor of a first conductivity type coupled between the first power source terminal and a first node, and including a first control gate coupled to a first terminal;

a second transistor of the first conductivity type coupled between the first power source terminal and a second node, and including a second control gate coupled to a second terminal;

a third transistor of a second conductivity type coupled between the first node and a third terminal, and including a third control gate coupled to the first node;

a fourth transistor of the second conductivity type coupled between the second node and the second power source terminal, and including a fourth control gate coupled to the first node; and

a fourth terminal coupled to the second node,

the method comprising:

applying a voltage potential difference as a reference voltage between the first and second terminals;

applying a target voltage to be detected to the third terminal; and

outputting an output signal from the fourth terminal which includes a comparison result between the reference voltage and a voltage difference between the target voltage and a potential at the second power source terminal.

14. The method according to claim 13 , wherein the first and second transistors have a same size, and

wherein the third and fourth transistors have a same size.

15. The method according to claim 13 , wherein a drain of the first transistor is coupled to a drain of the third transistor such that a current passing through the first transistor passes through the third transistor.

16. The method according to claim 13 , wherein different potentials are applied to the first control gate and the second control gate.

17. The method according to claim 13 , wherein the reference voltage is independent of a threshold voltage of the third transistor.