Watchdog timer and control method therefor

1. A watchdog timer, comprising:

a first register that stores a first overflow time;

a second register that stores a second overflow time; and

a counter that continues to count a clock signal to the first overflow time as long as a value of a program counter of a central processing unit (CPU) corresponds to a predetermined address, and that continues to count the clock signal to the second overflow time as long as the value of the program counter does not correspond to the predetermined address; wherein the counter clears a count value when the value of the program counter changes from another address to the predetermined address or changes from the predetermined address to another address; a third register that stores a permission information, wherein, the counter continues to count the clock signal to the second overflow time as long as the permission information indicates an inhibition state and the value of the program counter corresponds to the predetermined address.

2. The watchdog timer according to claim 1 , further comprising:

an address detector that compares the value of the program counter with the predetermined address to generate a signal,

wherein the counter counts the clock signal to the first overflow time if the signal has a first level, and counts the clock signal to the second overflow time if the signal has a second level different from the first level.

3. The watchdog timer according to claim 1 , further comprising:

a selector that outputs, according to the value of the program counter, one of the first and second overflow times to the counter.

4. The watchdog timer according to claim 1 , further comprising:

a counter clear controller that generates a clear signal when the value of the program counter changes from another address to the predetermined address or changes from the predetermined address to another address, wherein

the counter clears the count value according to the clear signal.

5. The watchdog timer according to claim 1 , further comprising:

a third register that stores a first address;

a fourth register that stores a second address,

wherein

the predetermined address comprises an address range from the first address to the second address and the counter counts the clock signal to the first overflow time if the value of the program counter is inside of the address range.

6. The watchdog timer according to claim 5 , further comprising:

an address detector that compares the value of the program counter with the address range, wherein

the counter counts the clock signal to one of the first and second overflow time in response to a comparison result of the address detector.

7. The watchdog timer according to claim 6 , wherein

the address detector includes:

a first comparator that compares the value of the program counter with the first address; and

a second comparator that compares the value of the program counter with the second address.

8. The watchdog timer according to claim 1 , wherein

the counter clears a count value according to a clear command output from the CPU.

9. The watchdog timer according to claim 1 , further comprising:

a counter clear controller that generates a clear signal when the value of the program counter changes from another address to the predetermined address or changes from the predetermined address to another address or the CPU outputs a clear command, wherein

the counter clears the count value according to the clear signal.

10. The watchdog timer according to claim 1 , wherein the first overflow time is longer than the second overflow time.

11. A microprocessor, comprising:

the watchdog timer according to claim 1 ; and

the CPU that is coupled to the watchdog timer.

12. The watchdog timer according to claim 1 ,

wherein the predetermined address comprises an address range from a first address to a second address, and

wherein the counter counts the clock signal to the first overflow time if the value of the program counter is inside of the address range.

13. The watchdog timer according to claim 12 ,

wherein the counter counts the clock signal to the second overflow time if the value of the program counter is outside of the address range.

14. A watchdog timer, comprising:

a counter,

wherein said counter:

continues to count a clock signal to a first overflow time as long as a value of a program counter of a central processing unit (CPU) corresponds to a predetermined address, and

continues to count the clock signal to a second overflow time as long as the value of the program counter does not correspond to the predetermined address, wherein the counter clears a count value when the value of the program counter changes from another address to the predetermined address or changes from the predetermined address to another address; and an overflow time selection section connected to said counter, wherein said overflow time selection section selects one of said first overflow time and said second overflow time based on an execution area signal and a permission setting signal.

15. The watchdog timer according to claim 14 , wherein when said execution area signal and said setting permission signal both comprise an active signal, said overflow time selection section outputs, to said counter, an overflow time signal indicating said first overflow time.

16. The watchdog timer according to claim 14 , wherein when at least one of said execution area signal and said setting permission signal comprise other than an active signal, said overflow time selection section outputs, to said counter, an overflow time signal indicating said second overflow time.

17. The watchdog timer according to claim 14 , further comprising:

an address matching detection section connected to said overflow time selection section,

wherein said address matching detection section outputs said execution area signal as an active signal when the value of the program counter corresponds to the predetermined address.