IP Library Granted Patent US 7,952,505
Granted Patent B2
US 7,952,505 · App. 12/659,231 · Granted May 31, 2011

Semiconductor device and input selection control method

Assignee: Renesas Electronics Corporation
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Quick Facts
Patent No.
US 7,952,505
App. No.
12/659,231
Granted
May 31, 2011
Kind
B2
Abstract

A semiconductor device includes: input terminals identified by channel numbers and configured to receive analog signals; analog input pads identified by pad numbers and connected with whole or part of the input terminals; a data holding section configured to hold a data of the input terminals; a channel designating section configured to generate a channel designation signal to designate one of the channel numbers; and a channel translating section configured to translate the channel number indicated by the channel designation signal into a specific one of the pad numbers based on the held data. An A/D converting section is configured to convert the analog signal inputted from the analog input pad corresponding to the specific pad number into a digital signal.

Claims (38)

1. A semiconductor device comprising:

input terminals identified by channel numbers and configured to receive analog signals;

analog input pads identified by pad numbers and connected with whole or part of said input terminals;

a data holding section configured to hold a data of said input terminals;

a channel designating section configured to generate a channel designation signal to designate one of the channel numbers;

a channel translating section configured to translate the channel number indicated by the channel designation signal into a specific one of the pad numbers based on the held data; and

an A/D converting section configured to convert the analog signal inputted from the analog input pad corresponding to the specific pad number into a digital signal.

2. The semiconductor device according to claim 1 , wherein the held data is set in said data holding section immediately after power is supplied, or before a user program is executed immediately after reset.

3. The semiconductor device according to claim 1 , further comprising:

an input signal selecting circuit configured to output one, which is selected based on the channel designation signal, of the analog signals inputted from said analog input pads.

4. The semiconductor device according to claim 1 , further comprising;

an input signal selecting circuit which comprises:

a decoder configured to decode the channel designation signal; and

a switch circuit configured to output the selected analog signal to said A/D converting section,

wherein said channel translating section translates an output of said decoder to supply to said switch circuit.

5. The semiconductor device according to claim 1 , wherein said channel designating section comprises:

a channel designation register configured to hold the channel number which is single; and

a channel designation counter configured to generate continuous channel numbers, and

wherein said channel designation counter changes a maximum count based on the held data.

6. The semiconductor device according to claim 1 , further comprising;

a result storage buffer configured to store the digital signal outputted from said A/D converting section in a location corresponding to the channel number based on said channel designation signal.

7. The semiconductor device according to claim 1 , further comprising;

a CPU configured to read out a digital data corresponding to the digital signal from said result storage buffer to execute a process.

8. The semiconductor device according to claim 7 , wherein said CPU sets the held data in said data holding section.

9. An input selection control method of selecting an analog signal to be subjected to A/D conversion in a semiconductor device which comprises:

a plurality of input terminals identified by channel numbers and configured to input analog signals;

analog input pad identified by pad numbers and connected with input terminals;

a data holding section configured to hold data of said plurality of input terminals; and

an A/D converting section configured to convert the analog signal inputted from the analog input pad corresponding to the designated pad number into a digital data, said input selection control method comprising:

generating a channel designation signal which specifies one of the channel numbers which identify the input terminals;

translating the channel number indicated by the channel designation signal into the pad number based on a data related to the input terminal; and

performing A/D conversion on an analog signal inputted from the analog input pad corresponding to the designated pad number to convert into a digital signal.

10. The input selection control method according to claim 9 , further comprising:

setting said data to a register immediately after a power is supplied or before a user program is executed immediately after a reset signal becomes active.

11. The input selection control method according to claim 9 , further comprising:

selecting one of the analog signals inputted from the analog input pads based on the channel designation signal to supply to said A/D converting section.

12. The input select control method according to claim 9 , further comprising;

storing said digital data in the location corresponding to the channel number of the result storage buffer based on the channel designation signal.

Assignments (3)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
CHANGE OF NAME Recorded Oct 26, 2010
From: NEC ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 025193/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 18, 2010
From: ISHIBUCHI, SOUICHIROU
To: NEC ELECTRONICS CORPORATION
Reel/Frame 024420/0244 →
Priority Claims (1)
JP 2009-048594 · Mar 2, 2009 · national
Continuity (1)
Related Publication 20100225516A1 · Sep 9, 2010