IP Library Granted Patent US 7,825,410
Granted Patent B2
US 7,825,410 · App. 12/659,734 · Granted Nov 2, 2010

Semiconductor device

Assignee: NEC Electronics Corporation
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,825,410
App. No.
12/659,734
Granted
Nov 2, 2010
Kind
B2
Abstract

A semiconductor device, includes a package substrate having a first surface and a second surface opposite to the first surface, and a semiconductor element installed in the first surface of the package substrate. The package substrate includes a plurality of first land pads disposed in the first surface, second land pads disposed in the second surface and a second testing-dedicated pad disposed in the second surface. The semiconductor element is electrically coupled to the first land pads, an inter-pad distance for the second land pads is larger than an inter-pad distance for the first land pads, the first land pad contains a first testing-dedicated pad electrically coupled to the semiconductor element, the first testing-dedicated pad and the second testing-dedicated pad each include a dedicated terminal, which is essential for applying a specified electrical signal from an LSI tester, when an LSI testing is conducted for a semiconductor wafer and the first testing-dedicated pad is electrically coupled to only the second testing-dedicated pad through a wiring.

Claims (24)

1. A semiconductor device, comprising:

a package substrate having a first surface and a second surface opposite to said first surface; and

a semiconductor element installed in said first surface of said package substrate,

wherein said package substrate includes a plurality of first land pads disposed in said first surface, second land pads disposed in said second surface and a second testing-dedicated pad disposed in said second surface,

said semiconductor element is electrically coupled to said first land pads,

an inter-pad distance for said second land pads is larger than an inter-pad distance for said first land pads,

a second land pad is provided with an external coupling terminal,

no external coupling terminal is provided in said second testing-dedicated pad,

said package substrate internally has a wiring,

a first land pad contains a first testing-dedicated pad electrically coupled to said semiconductor element,

said first testing-dedicated pad and said second testing-dedicated pad each comprises a dedicated terminal, which is essential for applying a specified electrical signal from an LSI tester, when an LSI testing is conducted for a semiconductor wafer, and

said first testing-dedicated pad is electrically coupled to only said second testing-dedicated pad through said wiring.

2. The semiconductor device, as set forth in claim 1 , wherein said first land pad is electrically coupled to said second land pad through said wiring.

3. The semiconductor device, as set forth in claim 1 , wherein said second testing-dedicated pad in said second surface is covered with an electrically insulating protective film.

4. The semiconductor device, as set forth in claim 3 , wherein said electrically insulating protective film comprises solder resist.

5. The semiconductor device, as set forth in claim 1 , wherein said semiconductor element is installed in said first surface of said package substrate through a bump.

6. The semiconductor device, as set forth in claim 1 ,

wherein said second land pads are disposed respectively in a circumference section and a central section of said second surface,

a space having a size larger than an inter-pad distance for said second land pads is formed between said circumference section and said central section, and

said second testing-dedicated pad is provided in said space.

7. The semiconductor device, as set forth in claim 1 ,

wherein said package substrate has a rectangular geometry, and

said second testing-dedicated pad is provided in at least one corner portion of said second surface.

8. The semiconductor device, as set forth in claim 1 , wherein said external coupling terminal comprises a solder bump.

Assignments (2)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
CHANGE OF NAME Recorded Oct 26, 2010
From: NEC ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 025193/0001 →
Priority Claims (1)
JP 2008-180610 · Jul 10, 2008 · national
Continuity (2)
Continuation 1232026300 · Jan 22, 2009
Related Publication 20100193787A1 · Aug 5, 2010