Group III-V nitride based semiconductor substrate and method of making same
View Patent ↗A group III-V nitride-based semiconductor substrate includes a group III-V nitride-based semiconductor crystal. A surface area of the substrate is greater than or equal to 45 cm 2 . A thickness of the substrate is greater than or equal to 200 μm. An in-plane dislocation density of the substrate is less than or equal to 2×10 7 cm −2 in average. The in-plane dislocation density of the substrate is less than or equal to 150% of the average at maximum.
1. A group III-V nitride-based semiconductor substrate, comprising:
a group III-V nitride-based semiconductor crystal, wherein a surface area of said substrate is greater than or equal to 45 cm 2 ,
wherein a thickness of said substrate is greater than or equal to 200 μm,
wherein an in-plane dislocation density of said substrate is less than or equal to 2×10 7 cm −2 in average,
wherein said in-plane dislocation density of said substrate is less than or equal to 150% of the average at maximum, and
wherein a dispersion of a crystal axis at a surface of said substrate is equal to or less than ±0.3 degrees.
2. A group III-V nitride-based semiconductor substrate, comprising:
a group III-V nitride-based semiconductor crystal,
wherein a surface area of said substrate is greater than or equal to 45 cm 2 , wherein a thickness of said substrate is greater than or equal to 200 μm,
wherein an in-plane dislocation density of said substrate is less than or equal to 2×10 7 cm −2 in average,
wherein said in-plane dislocation density of said substrate is less than or equal to 150% of the average at maximum, and
wherein a carrier concentration at an arbitrary point on a surface of said substrate is within a range of ±20% of an average carrier concentration at the surface.
3. The group III-V nitride-based semiconductor substrate according to claim 1 , wherein a thickness at an arbitrary surface of said substrate is within a range of ±10 μm from an average thickness at the surface.
4. The group III-V nitride-based semiconductor substrate according to claim 1 , wherein a diameter of said substrate is greater than or equal to 3 inches.
5. The group III-V nitride-based semiconductor substrate according to claim 1 , wherein a carrier concentration at an arbitrary point of said substrate is within a range of ±20% of an average carrier concentration at a surface.
6. The group III-V nitride-based semiconductor substrate according to claim 5 , wherein a full width at half maximum (FWHM) value of X-ray rocking curve of said group III-V nitride-based semiconductor crystal is less than or equal to 250 seconds.
7. The group III-V nitride-based semiconductor substrate according to claim 6 , wherein a full width at half maximum (FWHM) value of X-ray rocking curve of said group III-V nitride-based semiconductor crystal is less than or equal to 40 seconds.
8. The group III-V nitride-based semiconductor substrate according to claim 7 , wherein a full width at half maximum (FWHM) value of X-ray rocking curve of said group III-V nitride-based semiconductor crystal is less than or equal to 30 seconds.
9. The group III-V nitride-based semiconductor substrate according to claim 1 , wherein said group III-V nitride-based semiconductor crystal comprises a composition of In x Al y Ga 1-x-y N (x≧0, y≧0, x+y≦1).
10. The group III-V nitride-based semiconductor substrate according to claim 9 , wherein said group III-V nitride-based semiconductor crystal consists of a composition of In x Al y Ga 1-x-y N (x≧0, y≧0, x+y≦1).
11. The group III-V nitride-based semiconductor substrate according to claim 1 , wherein the dispersion of the crystal axis is generated during growth of the semiconductor substrate.
12. The group III-V nitride-based semiconductor substrate according to claim 1 , wherein the substrate is formed by the following process:
forming a group III-V nitride-based semiconductor underlying layer on a thick sapphire substrate;
growing a Si-doped group III-V nitride-based semiconductor thick film on the underlying layer; and
irradiating a laser from a backside of the sapphire substrate to separate the group III-V nitride-based semiconductor substrate from a remainder of the Si-doped group III-V nitride-based semiconductor thick film.
13. The group III-V nitride-based semiconductor substrate according to claim 12 , wherein the forming of the underlying layer comprises forming the underlying layer on a c-face of the sapphire substrate by metal oxide vapor phase epitaxy (MOVPE), the sapphire substrate having a diameter of 7.62 cm and a thickness of 650 μm.
14. The group III-V nitride-based semiconductor substrate according to claim 12 , further comprising:
forming a carbon layer on a back face of a sapphire substrate.
15. The group III-V nitride-based semiconductor substrate according to claim 1 , wherein the substrate is formed by the following process:
forming a group III-V nitride-based semiconductor underlying layer on a sapphire substrate;
forming a titanium layer on the underlying layer;
bonding the sapphire substrate to a susceptor;
thermally treating the titanium layer to nitride the titanium layer and form a titanium nitride nano-mask on the underlying layer, and form voids in the underlying layer, the voids reaching the sapphire substrate;
growing a group III-V nitride-based semiconductor thick film on the titanium nitride nano-mask; and
cooling the group III-V nitride-based semiconductor thick film to separate the group III-V nitride-based semiconductor substrate from a remainder of the group III-V nitride-based semiconductor thick film.
16. The group III-V nitride-based semiconductor substrate according to claim 1 , wherein the substrate is formed by the following process:
forming a group III-V nitride-based semiconductor underlying layer on a sapphire substrate;
forming a titanium layer on the underlying layer;
securing the sapphire substrate to a susceptor using a ring-shaped jig;
thermally treating the titanium layer to nitride the titanium layer and form a titanium nitride nano-mask on the underlying layer, and form voids in the underlying layer, the voids reaching the sapphire substrate;
growing a group III-V nitride-based semiconductor thick film on the titanium nitride nano-mask; and
cooling the group III-V nitride-based semiconductor thick film to separate the group III-V nitride-based semiconductor substrate from a remainder of the group III-V nitride-based semiconductor thick film.
17. A group III-V nitride-based semiconductor substrate, comprising:
a group III-V nitride-based semiconductor crystal, a surface area of said crystal being greater than or equal to 45 cm 2 , a thickness of said crystal being greater than or equal to 200 μm, and an in-plane dislocation density of said crystal being less than or equal to 2×10 7 cm −2 in average,
wherein the in-plane dislocation density of the crystal is substantially uniform at a central portion of the crystal and an outermost portion of the crystal, such that a maximum value of the in-plane dislocation density is less than or equal to 150% of an average value of the in-plane dislocation density, and
wherein a carrier concentration of the crystal is substantially uniform at a central portion of the crystal and an outermost portion of the crystal, such that a value of the carrier concentration at an arbitrary point on a surface of said crystal is within a range of ±20% of an average value of the carrier concentration at the surface.