IP Library Granted Patent US 8,420,445
Granted Patent B2
US 8,420,445 · App. 12/667,185 · Granted Apr 16, 2013

Method for packing semiconductor components and product produced according to the method

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Quick Facts
Patent No.
US 8,420,445
App. No.
12/667,185
Granted
Apr 16, 2013
Kind
B2
Abstract

A method for packing semiconductor components is provided, in which a first side of a first wafer is connected to at least one further wafer, wherein at least one of the wafers has a plurality a semiconductor circuits and wherein trenches are made in the second side of the first wafer opposite to the first side and divide the first wafer into a plurality of parts, which are separated from one another by the trenches, but are connected mechanically to one another by means of the at least one further wafer, and wherein the connecting region between the first wafer and the at least one further wafer has been or will be laterally exposed in the trenches. A coating that covers the connecting region is then applied to the regions of the trenches in which the connecting region is exposed.

Claims (10)

1. A method for packing of components on wafer surfaces, comprising:

connecting a first side of a first wafer to a first side of a second wafer, wherein at least one of the first and second wafers has a plurality of active components on the first side and wherein at least one of the first and second wafers has depressions extending on the first side so that the depressions form channels along a connecting surface region to cavities in the first and/or second wafers, the cavities at least partially surrounding the plurality of active components;

dividing the first wafer into a plurality of parts by making trenches in a second side of the first wafer opposite to the first side, the plurality of parts being separated from one another by the trenches, but being connected mechanically to one another by the second wafer, wherein the connecting surface region between the first and second wafer is laterally exposed in the trenches so that the channels open laterally into the trenches;

applying a coating to regions of the trenches in which the connecting surface region is exposed to cover the channels; and

wherein dividing the first wafer into the plurality of parts by making the trenches takes place prior to connecting the first and second wafers.

2. The method according to claim 1 , wherein said plurality of active components comprises semiconductor circuits.

3. The method according to claim 1 , further comprising forming the channels through at least one of the first and second wafers so that the channels run transversely to the connecting surface region so that the channels connect the cavity with the surroundings.

4. The method according to claim 1 , further comprising fixing the first wafer in place on an auxiliary substrate, then dividing first wafer into the plurality of parts so that the plurality of parts are connected to one another by the auxiliary substrate, and then connecting the first and second wafers.

5. The method according to claim 1 , further comprising

separating the second wafer along the trenches to produce a plurality of semiconductor components.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 1, 2010
From: SCHOTT ELECTRONIC PACKAGING ASIA PTE. LTD.
To: WAFER-LEVEL PACKAGING PORTFOLIO LLC
Reel/Frame 025077/0418 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 30, 2010
From: SCHOTT AG
To: SCHOTT ELECTRONIC PACKAGING ASIA PTE. LTD.
Reel/Frame 025074/0655 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 20, 2010
From: LEIB, JUERGEN
To: SCHOTT AG
Reel/Frame 024715/0882 →