Anti-fuse element
View Patent ↗Programmable anti-fuse circuitry including at least one anti-fuse cell having a first anti-fuse device coupled between a supply voltage and a first node and a second anti-fuse device coupled between the first node and a ground voltage, and control logic coupled to the first node and arranged to generate a programming voltage having one of at least a first voltage level for breaking-down the first anti-fuse device but not the second anti-fuse device and coupling the first node to the supply voltage; and a second voltage level for breaking-down the second anti-fuse device but not the first anti-fuse device and coupling the first node to the ground voltage.
1. Programmable anti-fuse circuitry comprising:
at least one anti-fuse cell comprising a first anti-fuse device coupled between a supply voltage and a first node and a second anti-fuse device coupled between the first node and a ground voltage; and
control logic coupled to the first node and arranged to generate a programming voltage having one of at least:
a first voltage level for breaking-down said first anti-fuse device but not said second anti-fuse device and coupling said first node to said supply voltage; and
a second voltage level for breaking-down said second anti-fuse device but not said first anti-fuse device and coupling said first node to said ground voltage;
wherein said first anti-fuse device comprises source and bulk regions coupled to said supply voltage and a drain region coupled to said first node, and wherein said second anti-fuse device comprises source and bulk regions coupled to said ground voltage and a drain region coupled to said first node.
2. The programmable anti-fuse circuitry of claim 1 , further comprising a MOS transistor having its gate coupled to said first node and arranged to sense the voltage at the first node.
3. A memory circuit comprising:
a plurality of memory blocks; and
programmable anti-fuse circuitry according to claim 1 , comprising at least one of said anti-fuse cells associated with each of said memory blocks, said control logic being arranged to control said anti-fuse cells to disconnect defective ones of said memory blocks.
4. A read only memory comprising an array of memory cells, each memory cell storing at least one bit of data, and comprising the programmable anti-fuse circuitry of claim 1 , wherein each memory cell comprises at least one of said anti-fuse cells for storing at least one bit of data.
5. A method of programming anti-fuse circuitry comprising at least one anti-fuse cell comprising first and second anti-fuse devices coupled to a first node, said first anti-fuse device also coupled to a supply voltage and said second anti-fuse device also coupled to a ground voltage, the method comprising:
applying a programming voltage at said first node for breaking-down one of said first and second anti-fuse devices, said programming voltage having one of at least two voltage levels comprising:
a first voltage level for breaking-down said first anti-fuse device but not said second anti-fuse device and coupling said first node to said supply voltage; and
a second voltage level for breaking-down said second anti-fuse device but not said first anti-fuse device and coupling said first node to said ground voltage;
wherein said first anti-fuse device comprises source and bulk regions coupled to said supply voltage and a drain region coupled to said first node, and wherein said second anti-fuse device comprises source and bulk regions coupled to said ground voltage and a drain region coupled to said first node.
6. Programmable anti-fuse circuitry comprising:
at least one anti-fuse cell comprising a first anti-fuse device coupled between a supply voltage and a first node and a second anti-fuse device coupled between the first node and a ground voltage; and
control logic coupled to the first node and arranged to generate a programming voltage having one of at least:
a first voltage level for breaking-down said first anti-fuse device but not said second anti-fuse device and coupling said first node to said supply voltage; and
a second voltage level for breaking-down said second anti-fuse device but not said first anti-fuse device and coupling said first node to said ground voltage;
wherein said first and second anti-fuse devices each comprise a gate coupled MOS device, said gate coupled MOS devices arranged such that said programming voltage causes snapback in one or the other of them.
7. Programmable anti-fuse circuitry comprising:
at least one anti-fuse cell comprising a first anti-fuse device coupled between a supply voltage and a first node and a second anti-fuse device coupled between the first node and a ground voltage; and
control logic coupled to the first node and arranged to generate a programming voltage having one of at least:
a first voltage level for breaking-down said first anti-fuse device but not said second anti-fuse device and coupling said first node to said supply voltage; and
a second voltage level for breaking-down said second anti-fuse device but not said first anti-fuse device and coupling said first node to said ground voltage;
wherein the first anti-fuse is formed of a gate-coupled p-channel MOS transistor, while the second anti-fuse is formed of a gate coupled n-channel MOS transistor.
8. Programmable anti-fuse circuitry comprising:
at least one anti-fuse cell comprising a first anti-fuse device coupled between a supply voltage and a first node and a second anti-fuse device coupled between the first node and a ground voltage; and
control logic coupled to the first node and arranged to generate a programming voltage having one of at least:
a first voltage level for breaking-down said first anti-fuse device but not said second anti-fuse device and coupling said first node to said supply voltage; and
a second voltage level for breaking-down said second anti-fuse device but not said first anti-fuse device and coupling said first node to said ground voltage;
wherein said supply voltage and ground voltage are chosen such that the voltage difference between said ground voltage and said supply voltage is lower than a minimum voltage for breaking-down either of said first and second anti-fuse devices, and wherein said first voltage level is lower than said ground voltage and said second voltage level is higher than said supply voltage.
9. A method of programming anti-fuse circuitry comprising at least one anti-fuse cell comprising first and second anti-fuse devices coupled to a first node, said first anti-fuse device also coupled to a supply voltage and said second anti-fuse device also coupled to a ground voltage, the method comprising:
applying a programming voltage at said first node for breaking-down one of said first and second anti-fuse devices, said programming voltage having one of at least two voltage levels comprising:
a first voltage level for breaking-down said first anti-fuse device but not said second anti-fuse device and coupling said first node to said supply voltage; and
a second voltage level for breaking-down said second anti-fuse device but not said first anti-fuse device and coupling said first node to said ground voltage;
further comprising, prior to applying said programming voltage, applying a soft programming voltage at said first node, said soft programming voltage being at one of two levels to simulate the effect of hard programming of said anti-fuse cell without causing break-down of said first and second anti-fuse devices.
10. A method of programming anti-fuse circuitry comprising at least one anti-fuse cell comprising first and second anti-fuse devices coupled to a first node, said first anti-fuse device also coupled to a supply voltage and said second anti-fuse device also coupled to a ground voltage, the method comprising:
applying a programming voltage at said first node for breaking-down one of said first and second anti-fuse devices, said programming voltage having one of at least two voltage levels comprising:
a first voltage level for breaking-down said first anti-fuse device but not said second anti-fuse device and coupling said first node to said supply voltage; and
a second voltage level for breaking-down said second anti-fuse device but not said first anti-fuse device and coupling said first node to said ground voltage;
comprising, after said step of applying said programming voltage, the step of reducing said supply voltage such that said supply voltage is lower than a voltage needed to break-down said anti-fuse devices.