IP Library Granted Patent US 8,115,552
Granted Patent B2
US 8,115,552 · App. 12/685,635 · Granted Feb 14, 2012

Amplifier circuit with step gain

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Quick Facts
Patent No.
US 8,115,552
App. No.
12/685,635
Granted
Feb 14, 2012
Kind
B2
Abstract

A step gain amplifier has an amplifier with an input and an output, and a bias circuit connected to the input and to a bias node. A passive feedback circuit using only passive elements connects the output to the input. A control circuit is connected to the bias circuit at the bias node.

Claims (27)

1. An amplifier system comprising: an amplifier having an input and an output, and a bias circuit; a passive feedback circuit comprising only passive elements connecting the output to the input; and a control circuit connected to the bias circuit,

wherein the amplifier has a first transistor coupled between the input and the output; and wherein the bias circuit is connected between the input and a bias node; and wherein the control circuit is connected to the bias node,

wherein the passive feedback circuit comprises a first resistor and a first capacitor coupled in series and a second resistor and a second capacitor connected in series and in series with the first resistor and the first capacitor, with the first capacitor connected to the input and the first resistor connected to the second resistor, and with the second capacitor connected to the output; and a third resistor connecting to the junction of the first resistor and the second resistor to ground.

2. The amplifier system of claim 1 , wherein the bias circuit comprises a second transistor having a second terminal coupled to the input, a third terminal connected to the bias node and a first terminal connected to ground, with the second terminal controlling the flow of current between the first and third terminals.

3. The amplifier system of claim 2 wherein the bias circuit further comprising: a third transistor, having a second terminal, a third terminal and a first terminal; wherein the second terminal of the third transistor is connected to the third terminal of the second transistor; the first terminal of the third transistor is connected to the second terminal of the second transistor; and the second terminal of the third transistor is coupled to a reference voltage.

4. The amplifier system of claim 3 wherein the third terminal of the third transistor is connected to a supply voltage.

5. An amplifier system comprising: an amplifier having an input and an output, and a bias circuit; a passive feedback circuit comprising only passive elements connecting the output to the input; and a control circuit connected to the bias circuit,

wherein the amplifier has a first transistor coupled between the input and the output; and wherein the bias circuit is connected between the input and a bias node; and wherein the control circuit is connected to the bias node,

wherein the bias circuit comprises a second transistor having a second terminal coupled to the input, a third terminal connected to the bias node and a first terminal connected to ground, with the second terminal controlling the flow of current between the first and third terminals, and

wherein the bias circuit further comprises a third transistor, having a second terminal, a third terminal and a first terminal; wherein the second terminal of the third transistor is connected to the third terminal of the second transistor; the first terminal of the third transistor is connected to the second terminal of the second transistor; and the second terminal of the third transistor is coupled with a reference voltage.

6. The amplifier system of claim 5 wherein the second transistor is of n-p-n bipolar type.

7. The amplifier system of claim 5 wherein the bias circuit further comprises a resistor connected between the second terminal of the third transistor and the reference voltage.

8. The amplifier system of claim 5 wherein the passive feedback circuit comprises a first resistor and a first capacitor coupled in series and a second resistor and a second capacitor connected in series and in series with the first resistor and the first capacitor, with the first capacitor connected to the input and the first resistor connected to the second resistor, and with the second capacitor connected to the output; and a third resistor connecting to the junction of the first resistor and the second resistor to ground.

9. The amplifier system of claim 5 wherein the third terminal of the third transistor is connected to a supply voltage.

10. The amplifier system of claim 1 wherein the control circuit comprises a resistor.

11. The amplifier system of claim 1 , wherein the control circuit further comprises: a resistor and a fourth transistor having a first terminal, a second terminal and a third terminal, with the first terminal connected to the bias node, the second terminal connected to the bias node and the third terminal connected to the resistor of the control circuit.

12. The amplifier system of claim 11 , wherein the control circuit further comprises: a fifth transistor having a first terminal, a second terminal, and a third terminal, with the first terminal of the fifth transistor connected to the third terminal of the fourth transistor and to the passive feedback circuit, the third terminal of the fifth transistor coupled to the input, and the second terminal of the fifth transistor connected to the passive feedback circuit.

13. The amplifier system of claim 5 , wherein the control circuit comprises a resistor.

14. The amplifier system of claim 5 , wherein the control circuit further comprises: a fourth transistor having a first terminal, a second terminal and a third terminal, with the first terminal connected to the bias node, the second terminal connected to the bias node and the third terminal connected to the resistor.

15. The amplifier system of claim 14 , wherein the control circuit further comprises: a fifth transistor having a first terminal, a second terminal, and a third terminal, with the first terminal of the fifth transistor connected to the third terminal of the fourth transistor and to the passive feedback circuit, the third terminal of the fifth transistor coupled to the input, and the second terminal of the fifth transistor connected to the passive feedback circuit.

16. An amplifier system comprising: an amplifier having an input and an output, and a bias circuit; a passive feedback circuit comprising only passive elements connecting the output to the input; and a control circuit connected to the bias circuit,

wherein the amplifier has a first transistor coupled between the input and the output; and

wherein the bias circuit is connected between the input and a bias node; and wherein the control circuit is connected to the bias node,

wherein the control circuit further comprises: a resistor and a second transistor having a first terminal, a second terminal and a third terminal, with the first terminal connected to the bias node, the second terminal connected to the bias node and the third terminal connected to the resistor of the control circuit.

17. The amplifier system of claim 16 , wherein the control circuit further comprises: a fifth transistor having a first terminal, a second terminal, and a third terminal, with the first terminal of the fifth transistor connected to the third terminal of the fourth transistor and to the passive feedback circuit, the third terminal of the fifth transistor coupled to the input, and the second terminal of the fifth transistor connected to the passive feedback circuit.

18. The amplifier system of claim 2 wherein the second transistor is of n-p-n bipolar type.

19. The amplifier system of claim 3 wherein the bias circuit further comprises a resistor connected between the second terminal of the third transistor and the reference voltage.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 059666/0545 →
RELEASE OF SECURITY INTEREST Recorded Feb 25, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059333/0222 →
SECURITY INTEREST Recorded Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
SECURITY INTEREST Recorded Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
SECURITY INTEREST Recorded Feb 10, 2017
From: MICROCHIP TECHNOLOGY INCORPORATED
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 041675/0617 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 3, 2011
From: SILICON STORAGE TECHNOLOGY, INC.
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 026213/0515 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 11, 2010
From: KOBAYASHI, BUN; SCHELL, STEVEN; KIM, YONGHAN CHRIS; CHOW, PEI-MING DANIEL; CHANG, MAU-CHUNG FRANK
To: SILICON STORAGE TECHNOLOGY, INC.
Reel/Frame 023762/0230 →