IP Library Granted Patent US 8,222,745
Granted Patent B2
US 8,222,745 · App. 12/689,806 · Granted Jul 17, 2012

Integrated heat sink

Assignee: LSI Corporation
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Quick Facts
Patent No.
US 8,222,745
App. No.
12/689,806
Granted
Jul 17, 2012
Kind
B2
Abstract

An electronic device includes a heat dissipating component located over a substrate. An isolation trench is formed in the substrate adjacent the component. A contact region of the substrate is bounded by the trench. An electrically isolated contact is located over and in contact with the contact region. The electrically isolated contact and the contact region provide a thermally conductive path to the substrate.

Claims (32)

1. An electronic device, comprising:

a heat dissipating component located over a substrate;

an isolation trench formed in said substrate adjacent said component;

a contact region of said substrate bounded by said trench; and

an electrically isolated contact located over and in connected to said contact region, said electrically isolated contact and said contact region providing a thermally conductive path to the substrate.

2. The device of claim 1 , further comprising an electrically isolated interconnect metal portion located over said contact region, wherein said electrically isolated contact is located between said interconnect metal portion and said contact region, said electrically isolated contact providing a thermally conductive path from said interconnect metal portion to said contact region.

3. The device of claim 1 , wherein said isolation trench is a first isolation trench, said contact region is a first contact region, and said electrically isolated contact is a first electrically isolated contact, and further comprising:

a second isolation trench located adjacent said component;

a second contact region bounded by said second isolation trench; and

a second electrically isolated contact connected to said second contact region,

wherein said component is interposed between said first and second contact regions.

4. The device of claim 3 , further comprising a first interconnect metal portion located over said first contact region and a second interconnect metal portion located over said second contact region, wherein said first contact is located between said first interconnect metal portion and said first contact region, and said second contact is located between said second interconnect metal portion and said second contact region.

5. The device of claim 4 , wherein said first and said second interconnect metal portions are a same interconnect metal portion.

6. The device of claim 1 , further comprising a via conductively coupled to said electrically isolated contact.

7. The device of claim 1 , wherein said electrically isolated contact is one of a plurality of electrically isolated contacts connected to said contact region.

8. The device of claim 7 , wherein said plurality of electrically isolated contacts is connected to a same interconnect metal portion.

9. The device of claim 1 , wherein said trench completely surrounds said contact region.

10. The device of claim 1 , wherein said component is a resistor.

11. A method of forming an electronic device, comprising:

providing a substrate having a heat-dissipating component located thereover, an isolation trench adjacent said component, and a contact region of the substrate bounded by said trench; and

locating an electrically isolated contact over and in contact with said contact region, said contact and said contact region providing a thermally conducting path to said substrate.

12. The method of claim 11 , further comprising locating an interconnect metal portion over said contact region, wherein said electrically isolated contact is located between said interconnect metal portion and said contact region, said electrically isolated contact providing a thermally conductive path from said interconnect metal portion to said contact region.

13. The method of claim 11 , wherein said isolation trench is a first isolation trench, said contact region is a first contact region, and said electrically isolated contact is a first electrically isolated contact, and further comprising:

locating a second isolation trench adjacent said component, the second isolation trench bounding a second contact region, wherein said component is interposed between said first and second contact regions; and

locating a second contact over and in contact with said second contact region.

14. The method of claim 13 , further comprising locating a first interconnect metal portion over said first contact region and locating a second interconnect metal portion over said second contact region, such that said first contact is located between said first interconnect metal portion and said first contact region, and said second contact is located between said second interconnect metal portion and said second contact region.

15. The method of claim 14 , wherein said first and said second interconnect metal portions are a same interconnect metal portion.

16. The method of claim 11 , further comprising forming a via that is conductively coupled to said electrically isolated contact.

17. The method of claim 11 , wherein said electrically isolated contact is one of a plurality of electrically isolated contacts each located adjacent said component.

18. The method of claim 17 , wherein said plurality of electrically isolated contacts is connected to a same interconnect metal portion.

19. The method of claim 11 , wherein said trench completely surrounds said contact region.

20. The method of claim 11 , wherein said component is a resistor.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 059723/0382 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044886/0766 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 19, 2010
From: PARK, SANGJUNE; IWASHITA, CARL
To: LSI CORPORATION
Reel/Frame 023811/0789 →
Continuity (1)
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