IP Library Granted Patent US 7,807,478
Granted Patent B2
US 7,807,478 · App. 12/690,831 · Granted Oct 5, 2010

Nonvolatile memory device and fabrication method thereof

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Quick Facts
Patent No.
US 7,807,478
App. No.
12/690,831
Granted
Oct 5, 2010
Kind
B2
Abstract

A nonvolatile memory device and its fabrication method of the present invention may ensure a margin of the threshold drive voltage during a design process of the device by forming a resistance layer determining phase of ReRAM along an upper edge of a lower electrode, and improve operating characteristics of the device

Claims (16)

1. A fabrication method of a nonvolatile memory device, comprising:

forming a first interlayer insulating film including a first electrode over a part of a semiconductor substrate;

forming a second interlayer insulating film including a contact hole exposing the first electrode over a part of the first interlayer insulating film;

forming a first resistance layer on sidewalls of the contact hole;

forming a second resistance layer filling up an inside of the first resistance layer;

forming a second electrode over the first and second resistance layers; and

forming a third interlayer insulating film with a contact plug overlapping with the first electrode over a part of the second electrode.

2. The method of claim 1 , wherein the first electrode and the second electrode are comprise platinum group elements.

3. The method of claim 2 , wherein the platinum group elements are selected from the group consisting of platinum (Pt), iridium (Ir), and metallurgical equivalents thereof.

4. The method of claim 1 , wherein the first resistance layer comprises an oxide containing niobium (Nb).

5. The method of claim 4 , wherein the oxide containing Nb principally comprises NbO 2 or Nb 2 O 5 .

6. The method of claim 1 , comprising forming the first resistance layer by a chemical vapor deposition (CVD) process.

7. The method of claim 1 , wherein the second resistance layer comprises a material having a threshold drive voltage for switching phase higher than a threshold drive voltage for switching phase of the first resistance layer.

8. The method of claim 1 , wherein the second resistance layer comprises an oxide containing aluminum (Al).

9. The method of claim 8 , wherein the oxide containing Al principally comprises Al 2 O 3 .

10. The method of claim 1 , comprising forming the second resistance layer by a chemical vapor deposition (CVD) process.

Assignments (4)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE IS HYNIX SEMICONDUCTOR INC. NOT HYNIX-SEMICONDUCTOR INC. THERE IS NO HYPHEN IN THE NAME. PREVIOUSLY RECORDED ON REEL 67328 FRAME 814. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded May 14, 2024
From: HYNIX SEMICONDUCTOR INC.
To: SK HYNIX INC.
Reel/Frame 067412/0482 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 9, 2024
From: SK HYNIX INC.
To: MIMIRIP LLC
Reel/Frame 067369/0832 →
CHANGE OF NAME Recorded May 6, 2024
From: HYNIX-SEMICONDUCTOR INC.
To: SK HYNIX INC.
Reel/Frame 067328/0814 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 24, 2017
From: KIM, TAE HOON
To: HYNIX SEMICONDUCTOR INC.
Reel/Frame 041366/0043 →