Semiconductor device
View Patent ↗A conventional semiconductor device has a problem that an on-current of a parasitic transistor flows through a surface portion of a semiconductor layer and thus a semiconductor element undergoes thermal breakdown. In a semiconductor device according to the present invention, a protection element is formed with use of an isolation region and N type buried layers. A PN junction region in the protection element is formed on a P type buried layer of the isolation region. The PN junction region has a junction breakdown voltage lower than that of a PN junction region of a semiconductor element to be protected. This structure allows an on-current of a parasitic transistor to flow into the protection element, and thereby the semiconductor element is protected. In addition, the on-current of the parasitic transistor flows through a deep portion of the epitaxial layer, and thereby the protection element is prevented from thermal breakdown.
1. A semiconductor device comprising:
a semiconductor layer;
an isolation region dividing the semiconductor layer into a plurality of element-formation regions;
a semiconductor element formed in a first element-formation region of the element-formation regions;
a first diffusion layer formed in the first element-formation region and forming a first PN junction region with the isolation region that defines the first element-formation region; and
a second diffusion layer formed in a second element-formation region of the element-formation regions, the first and second element-formation regions being disposed next to each other so as to be divided by the isolation region, and different voltages being applied to the first and second diffusion layers,
wherein a junction breakdown voltage of the first PN junction region is lower than a junction breakdown voltage of an element PN junction region included in the semiconductor element,
the first and second diffusion layers are each disposed at a bottom portion of the semiconductor layer and each have a lower resistance than the semiconductor layer, and
at a time of breakdown, a current path is formed between the first and second diffusion layers through the isolation region.
2. The semiconductor device of claim 1 , wherein the second diffusion layer is in contact with the isolation region so as to form a second PN junction region with the isolation region.
3. The semiconductor device of claim 1 , wherein the isolation region comprises an upper portion and a lower portion that has a higher impurity concentration than the upper portion of the isolation region, and the lower portion of the isolation region is in contact with the first and second diffusion layers.
4. The semiconductor device of claim 1 , wherein the isolation region comprises an upper portion comprising an insulating film and a lower portion comprising a diffusion layer, and the lower portion of the isolation region is in contact with the first and second diffusion layers.
5. The semiconductor device of claim 1 , wherein the first PN junction region surrounds the first element-formation region in plan view of the semiconductor layer.
6. The semiconductor device of claim 3 , wherein the first PN junction region comprises a PN junction between the lower portion of the isolation region and the first diffusion layer.
7. The semiconductor device of claim 1 , wherein the semiconductor element is a bipolar transistor, a MOS transistor or a diffused resistor.
8. A protection element of a semiconductor device, comprising:
a first semiconductor layer of a first general conductivity type;
a second semiconductor layer of the first general conductivity type disposed on the first semiconductor layer and having an impurity concentration lower than the first semiconductor layer;
a third semiconductor layer of the first general conductivity type disposed adjacent the first semiconductor layer;
a fourth semiconductor layer of the first general conductivity type disposed on the third semiconductor layer and having an impurity concentration lower than the third semiconductor layer;
a first contact diffusion layer of the first general conductivity type formed in the second semiconductor layer so as to be in contact with the first semiconductor layer and having an impurity concentration higher than the second semiconductor layer;
a second contact diffusion layer of the first general conductivity type formed in the fourth semiconductor layer so as to be in contact with the third semiconductor layer and having an impurity concentration higher than the fourth semiconductor layer; and
an isolation region isolating the first and second semiconductor layers from the third and fourth semiconductor layers and being in contact with the first and third semiconductor layers,
wherein the first contact diffusion layer receives a power potential or ground potential, and the second contact diffusion layer receives the power potential or the ground potential that is not received by the first contact diffusion layer.