Insulated gate semiconductor device
View Patent ↗A two-layer electrode structure is provided. A protection diode is provided not to overlap a gate pad portion. Cells and a first one of source electrode layers can be provided below the gate pad portion, so that the differences in resistance among various points in the source electrode layers can be decreased. In addition, the protection diode is positioned adjacent to a device region and at an end portion, of a chip, outward of the device region in such a way as to be in the closest proximity to the gate pad portion. A larger device region with efficient transistor operation can thus be secured, and the resistance of the first source electrode layer below a wiring portion can be reduced.
1. An insulated gate semiconductor device comprising:
a semiconductor substrate;
a device region which is a region of the semiconductor substrate in which a plurality of cells of insulated gate transistors are formed, each of the transistors includes a source region;
a first top terminal electrode layer disposed on the semiconductor substrate so as to cover a first portion of the device region, the first top terminal electrode layer being electrically connected to the device region but not being in direct physical contact with the first portion, the first portion having the cells formed therein;
a second top terminal electrode layer disposed on the semiconductor substrate so as to cover a second portion of the device region, the second top terminal electrode layer being electrically connected to the device region but not being in direct physical contact with the second portion, the second portion having the cells formed therein, the second top terminal layer comprising a pad portion to which an electrical connection is made to receive a control signal for the transistors in the device region; and
a protection diode formed in the semiconductor substrate so as to be outside the device region but adjacent the device region,
wherein in plan view of the semiconductor substrate the pad portion and the protection diode do not overlap,
the protection diode is disposed in a peripheral region of the semiconductor substrate and extends along at least one side of the semiconductor substrate,
the cells are disposed below the pad portion so that the cells and the pad portion overlap in plan view of the semiconductor substrate, and
the source regions of the transistors are disposed below the pad portion so that the source regions and the pad portion overlap in plan view of the semiconductor substrate.
2. The insulated gate semiconductor device of claim 1 , wherein the second top terminal electrode layer comprises a wiring portion that connects the pad portion and a portion of the second top terminal electrode layer covering the protection diode with the shortest distance between the pad portion and the portion covering the protection diode.
3. The insulated gate semiconductor device of claim 1 , further comprising a first bottom terminal electrode layer disposed between the first top terminal electrode layer and the device region so as to cover the entire device region and be electrically connected to the first top terminal electrode layer, and a second bottom terminal electrode layer disposed between the second top terminal electrode layer and the protection diode so as to be outside the device region and be electrically connected to the second top terminal electrode layer.
4. The insulated gate semiconductor device of claim 3 , wherein a first end of the protection diode is in contact with the first bottom terminal electrode layer, and a second end of the protection diode is in contact with the second bottom terminal electrode layer.
5. The insulated gate semiconductor device of claim 3 , wherein the second top terminal electrode layer comprises a wiring portion that connects the pad portion and a portion of the second top terminal electrode layer covering the protection diode, and the portion covering the protection diode is in contact with the second bottom terminal electrode layer.
6. The insulated gate semiconductor device of claim 5 , wherein the cells are provided below the wiring portion.
7. An insulated gate semiconductor device comprising:
a semiconductor substrate;
a device region which is a region of the semiconductor substrate in which a plurality of cells of insulated gate transistors are formed, each of the transistors includes a source region;
a protection diode formed in the semiconductor substrate so as to be outside the device region but adjacent the device region;
a first bottom terminal electrode layer covering the entire device region;
a second bottom terminal electrode layer covering the protection diode;
a first top terminal electrode layer disposed on and connected to the first bottom terminal electrode layer; and
a second top terminal electrode layer disposed on and connected to the second bottom terminal electrode layer and extending from a region above the protection diode to cover part of the first bottom terminal electrode layer,
wherein the second top terminal electrode layer comprises a pad portion to which an electrical connection is made to receive a control signal for the transistors in the device region,
the source regions of the transistors are disposed below the pad portion so that the source regions and the pad portion overlap in plan view of the semiconductor substrate, and
in plan view of the semiconductor substrate the pad portion and the protection diode do not overlap.