Data transfer system
View Patent ↗The invention is directed to decreasing a circuit size of a system in which a plurality of devices or circuit blocks share and use one memory. A system is configured so that a memory block serves as a master and each of circuit blocks serves as a slave, and thus the slave side (the circuit blocks) receives necessary data from the memory block by only having decoders corresponding to addresses assigned thereto in advance and registers. In this case, since the registers have been also needed in a conventional system in order to hold data read out from a memory, the circuit size decreases in the whole system. Since this effect is enhanced in proportion to the number of the circuit blocks sharing the memory block, the effect is enhanced as the system size increases.
1. A data transfer system comprising:
a plurality of system components, each of the system components being a circuit block or a device; and
a memory shared and used by the system components,
wherein the memory comprises a plurality of memory areas, each of the memory areas holding data corresponding to a plurality of memory addresses, and a memory control circuit outputting the memory addresses and the data held corresponding to the memory addresses in synchronization with a clock,
each of the system components comprises a decoder decoding a memory address outputted by the memory control circuit so as to determine whether said memory address corresponds to one of the memory addresses that are assigned in advance to the system component, and a register receiving the data outputted by the memory control circuit in synchronization with the clock depending on a result of the decoding by the decoder, and
the memory control circuit starts the outputting of the memory addresses and the data in response to at least part of the data held in the memory areas being rewritten.
2. The data transfer system of claim 1 , further comprising an automatic lead trigger circuit starting the outputting of the memory addresses and the data by the memory control circuit when the memory is powered on.
3. The data transfer system of claim 1 , further comprising an automatic lead trigger circuit starting the outputting of the memory addresses and the data by the memory control circuit in response to a trigger signal from the circuit block.
4. The data transfer system of claim 1 , wherein the memory control circuit starts the outputting of the memory addresses and the data at a regular interval.
5. The data transfer system of claim 1 , wherein the memory control circuit comprises an address counter increasing a memory address in synchronization with the clock.
6. The data transfer system of claim 1 , wherein the memory and the system components are formed on one semiconductor chip.