Substrates having voltage switchable dielectric materials
Various aspects provide for incorporating a VSDM into a substrate to create an ESD-protected substrate. In some cases, a VSDM is incorporated in a manner that results in the ESD-protected substrate meeting one or more specifications (e.g., thickness, planarity, and the like) for various subsequent processes or applications. Various aspects provide for designing a substrate (e.g., a PCB) incorporating a VSDM, and adjusting one or more aspects of the substrate to design a balanced, ESD-protected substrate. Certain embodiments include molding a substrate having a VSDM layer into a first shape.
1. A printed circuit board having:
one or more prepreg lavers;
a first region including a voltage switchable dielectric material; and
a flatness within one or more IPC standards for flatness; a balance region that offsets an imbalance in the printed circuit board associated with the first region.
2. The printed circuit board of claim 1 , wherein at least one standard includes a specification associated with IPC-4101A.
3. The printed circuit board of claim 1 , wherein a stacking of the prepreg layers is not characterized by mirror symmetry with respect to a centerline associated with the stacking of the prepreg layers.
4. The printed circuit board of claim 1 , wherein a stacking of the prepreg layers is not characterized by mirror symmetry with respect to a centerline associated with the printed circuit board.
5. The printed circuit board of claim 1 , wherein any of the first region and balance region is substantially planar.
6. The printed circuit board of claim 1 , wherein the first region and at least a portion of the balance region are on opposite sides of a centerline of the printed circuit board.
7. The printed circuit board of claim 6 , wherein the first region and the portion of the balance region are the same distance from the centerline.
8. The printed circuit board of claim 6 , wherein the portion of the balance region is a greater distance from the centerline than the first region.
9. The printed circuit board of claim 1 , wherein the first region and at least a portion of the balance region are on the same side of a centerline.
10. The printed circuit board of claim 1 , wherein at least a portion of the balance region is a smaller or larger distance from a centerline than the first region.
11. The printed circuit board of claim 1 , wherein the first region is characterized by a first thermal expansion coefficient, and the balance region is characterized by a second thermal expansion coefficient.
12. The printed circuit board of claim 1 , wherein the balance region includes at least one prepreg layer.
13. The printed circuit board of claim 12 , wherein first and second prepreg layers are on the same side of a centerline.
14. The printed circuit board of claim 12 , wherein first and second prepreg layers are on opposite sides of a centerline.
15. The printed circuit board of claim 12 , wherein a first prepreg layer has a higher resin content than a second prepreg layer.
16. The printed circuit board of claim 12 , wherein a first prepreg layer has a larger artwork compensation specification than that of a second prepreg layer.
17. The printed circuit board of claim 12 , wherein each of a first and a second prepreg layer is characterized by an artwork compensation specification, and a difference between the artwork compensation specifications is greater than 0.0001 inches per inch of length in a grain direction associated with the respective prepreg layers.
18. The printed circuit board of claim 12 , wherein a first prepreg layer has a smaller diameter reinforcement than that of a second prepreg layer.
19. The printed circuit board of claim 12 , wherein at least a portion of a reinforcement associated with a first prepreg layer is of a different composition, size, or weave than that associated with a second prepreg layer.
20. The printed circuit board of claim 12 , wherein at least one prepreg layer includes a style 106 prepreg layer.
21. The printed circuit board of claim 12 , wherein first and second prepreg layers have different thicknesses.
22. The printed circuit board of claim 12 , wherein first and second prepreg layers have different basis weights.
23. The printed circuit board of claim 12 , wherein the balance region includes a polymer.
24. The printed circuit board of claim 23 , wherein the polymer includes a filled polymer.
25. The printed circuit board of claim 24 , wherein the filled polymer includes a second voltage switchable dielectric material.