Granted Patent B2

US 8,300,487 · App. 12/695,364 · Granted Oct 30, 2012

Abstract

Claims (15)

1. A semiconductor device comprising: a plurality of terminals; a plurality of drive units corresponding to said plurality of terminals; and a data control unit which outputs parallel data applied to said plurality of terminals to said plurality of drive units in a normal operation mode, and which converts serial data applied to a particular terminal, which is one of said plurality of terminals, to parallel data, to output the parallel data to which the serial data applied to the particular terminal is converted to said plurality of drive units in a test mode, wherein said data control unit includes:

a serial/parallel conversion unit which converts the serial data applied to said particular terminal to parallel data and outputs the parallel data; and

a switch unit which outputs the parallel data applied to said plurality of terminals to said plurality of drive units in the normal operation mode, and outputs the parallel data output from said serial/parallel conversion unit to said plurality of drive units in the test mode.

2. A semiconductor device comprising: a plurality of terminals; a plurality of drive units corresponding to said plurality of terminals; and a data control unit which outputs parallel data applied to said plurality of terminals to said plurality of drive units in a normal operation mode, and which converts serial data applied to a particular terminal, which is one of said plurality of terminals, to parallel data, to output the parallel data to which the serial data applied to the particular terminal is converted to said plurality of drive units in a test mode, wherein each of said drive units comprises a write unit which writes information into a memory cell area based on data applied from said data control unit.

3. The semiconductor device according to claim 1 , wherein each of said drive units comprises a write unit which writes information into a memory cell area based on data applied from said data control unit.

4. A device comprising:

a plurality of terminals;

a plurality of drive units provided correspondingly to the terminals;

a data control circuit including a first input node coupled to one of the terminals and a plurality of first output nodes, the data control circuit being configured to respond to data supplied to the first input node from the one of the terminals and produce data at first output nodes, respectively; and

a switch circuit including a plurality of second input nodes each coupled to an associated one of the terminals, a plurality of third input nodes each coupled to an associated one of the first output nodes of the data control circuit and a plurality of second output nodes each coupled to an associated one of the drive units, the switch circuit being configured to electrically connect each of the second output nodes to an associated one of the second input nodes in a normal operation mode and to an associated one of the third input nodes in a test mode.

5. The device as claimed in claim 4 , wherein each of the drive units comprises a write unit that writes information into a memory cell area in response to a signal from an associated one of the terminals in the normal operation mode and from an associated one of the second output nodes of the data control circuit in the test mode.

6. The device as claimed in claim 4 , wherein the data control circuit comprises a serial/parallel conversion unit to convert the serial data from the one of the terminals to the parallel data.

7. The device as claimed in claim 6 , wherein the data control circuit further comprises a counter controlling the serial/parallel conversion unit.

8. The device as claimed in claim 4 , further comprising a memory cell area that comprises a plurality of sense amplifiers each operatively coupled to an associated one of the drive units and a plurality of memory cells each operatively coupled to an associated one of the sense amplifiers.

9. The device as claimed in claim 4 , further comprising a plurality of buffer circuits each inserted between an associated one of the terminals and an associate one of the second input nodes of the switch circuit.

Assignments (9)