Self-aligned SI rich nitride charge trap layer isolation for charge trap flash memory
View Patent ↗A method for fabricating a memory device with U-shaped trap layers over rounded active region corners is disclosed. In the present invention, an STI process is performed before the charge-trapping layer is formed. Immediately after the STI process, the sharp corners of the active regions are exposed, making them available for rounding. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, a bottom oxide layer, nitride layer, and sacrificial top oxide layer are formed. An organic bottom antireflective coating applied to the charge trapping layer is planarized. Now the organic bottom antireflective coating, sacrificial top oxide layer, and nitride layer are etched, without etching the sacrificial top oxide layer and nitride layer over the active regions. After the etching the charge trapping layer has a cross-sectional U-shape appearance. U-shaped trap layer edges allow for increased packing density and integration while maintaining isolation between trap layers.
1. A method for manufacturing a memory device, the method comprising:
performing a shallow trench isolation process on a semiconductor material to form an active region and an isolation region;
forming a charge trapping structure over the entire active region, wherein the charge trapping structure is self-aligned, wherein the charge trapping structure is substantially U-shaped over the entire active region, and wherein the charge trapping structure is a single U-shape; and
forming a first layer of semiconductor or conductive material over the charge trapping structure.
2. The method of claim 1 , wherein the charge trapping structure is self-aligned by:
fabricating a bottom oxide layer;
depositing a SiRN layer;
depositing a sacrificial top oxide layer;
depositing an organic bottom antireflective coating, wherein the organic bottom antireflective coating is planarized;
etching to separate the SiRN layer between a plurality of cells, wherein the sacrificial top oxide layer and the SiRN layer are not etched over the active regions.
3. The method of claim 1 further comprising:
performing the shallow trench isolation process before forming the charge trapping structure to expose corners of the active region so that the exposed corners can be rounded through a rounding process.
4. The method of claim 1 , wherein forming the charge trapping structure comprises:
forming a bottom oxide layer over the active region
forming a nitride layer over the bottom oxide layer
forming a top conformal oxide layer over the nitride layer.
5. The method of claim 1 , wherein the sacrificial top oxide layer is between 20-100 angstroms (Å) thick.
6. The method of claim 2 , wherein the organic bottom antireflective coating is replaced with other materials suitable for use in planarization.
7. The method of claim 3 , further comprising performing at least one liner oxide process to round the exposed corners of the active region.
8. The method of claim 3 , further comprising performing at least one cleaning process to round the exposed corners of the active region.
9. The method of claim 4 , wherein the nitride layer is comprised of silicon rich nitride.
10. The method of claim 4 , wherein the nitride layer is comprised of nitride on top of silicon rich nitride.
11. The method of claim 4 , wherein the nitride layer is comprised of multiple layers of nitride having different percentages of silicon content.