Insulated-gate semiconductor device with protection diode
View Patent ↗Channel regions continuous with transistor cells are disposed also below a gate pad electrode. The channel region below the gate pad electrode is fixed to a source potential. Thus, a predetermined reverse breakdown voltage between a drain and a source is secured without forming a p+ type impurity region below the entire lower surface of the gate pad electrode. Furthermore, a protection diode is formed in a conductive layer disposed at the outer periphery of an operation region.
1. A transistor device comprising a protection diode device, comprising:
a semiconductor substrate;
a transistor formed on the semiconductor substrate;
a gate pad electrode disposed on the semiconductor substrate and connected to the transistor;
a source electrode disposed on and connected to the transistor;
a first diode series comprising a plurality of pn junctions connected serially, one end of the first diode series being connected to the gate pad electrode and another end of the first diode series being connected to the source electrode; and
a second diode series comprising a plurality of pn junctions connected serially, one end of the second diode series being connected to the gate pad electrode and another end of the second diode series being connected to the source electrode,
wherein the first diode series and the second diode series are aligned along an edge of the semiconductor substrate, the edge extending in a first direction, and
all of the pn junctions in the first diode series and the second diode series are aligned parallel in a second direction that is different from the first direction.
2. The transistor device of claim 1 , wherein, in plan view of the semiconductor substrate, the first and second diode series form a line along an edge of the semiconductor substrate and is disposed between the gate pad electrode and the edge of the semiconductor substrate.
3. The transistor device of claim 1 , further comprising a third diode series comprising a plurality of pn junctions connected serially, one end of the third diode series being connected to the another end of the first diode series and another end of the third diode series being connected to the gate pad electrode.
4. The transistor device of claim 3 , further comprising a gate wiring connecting the gate pad electrode and the another end of the third diode series, wherein, in plan view of the semiconductor substrate, the first, second and third diode series form a line along an edge of the semiconductor substrate, and the gate wiring is disposed between the line and the edge of the semiconductor substrate.
5. The transistor device of claim 1 , further comprising a gate wiring connecting the gate pad electrode and the one end of the second diode series, wherein, in plan view of the semiconductor substrate, the first and second diode series form a line along an edge of the semiconductor substrate, and the gate wiring is disposed between the line and the edge of the semiconductor substrate.
6. The transistor device of claim 5 , further comprising a third diode series comprising a plurality of pn junctions connected serially, one end of the third diode series being connected to the one end of the first diode series and another end of the third diode series being connected to the source electrode, wherein the third diode series extends from the line.
7. The transistor device of claim 1 , further comprising a third diode series comprising a plurality of pn junctions connected serially, one end of the third diode series being connected to the another end of the first diode series and another end of the third diode series being connected to the gate pad electrode, and a fourth diode series comprising a plurality of pn junctions connected serially, one end of the fourth diode series being connected to the another end of the second diode series and another end of the fourth diode series being connected to the gate pad electrode.
8. The transistor device of claim 7 , further comprising a gate wiring connecting the gate pad electrode and the another ends of the third and fourth diode series, wherein, in plan view of the semiconductor substrate, the first, second, third and fourth diode series form a line along an edge of the semiconductor substrate, and the gate wiring is disposed between the line and the edge of the semiconductor substrate.
9. The transistor device of claim 1 , wherein the second direction is substantially perpendicular to the first direction.