Low couple effect bit-line voltage generator
A bit-line voltage generator is provided. The bit-line voltage generator includes a discharge enhanced bias source and a switch unit. The switch unit includes a clamp transistor having a source, a gate connected to the discharge enhanced bias source, and a drain receiving a voltage; a switch transistor having a gate receiving a control signal, a drain connected to the source of the clamp transistor, and a source connected to a memory array, wherein a parasitic capacitor exists between the gate and the source of the clamp transistor; a resistor having a first terminal connected to the drain of the switch transistor, and a second terminal connected to ground; and a capacitor having a first terminal connected to the drain of the switch transistor, and a second terminal connected to ground, wherein a charge in the parasitic capacitor, when the switch transistor is turned on, is almost identical to that when the switch transistor is turned off, so that a couple effect between the switch unit and the discharge enhanced bias source is reduced, thereby stabilizing a bias applied to the memory array.
1. A switch unit, comprising:
a first transistor having a source, a gate connected to a discharge bias source, and a drain receiving a voltage;
a second transistor having a gate receiving a control signal, a drain connected to the source of the first transistor, and a source connected to a memory array, wherein a parasitic capacitor exists between the gate and the source of the first transistor;
a resistor having a first terminal connected to the drain of the second transistor, and a second terminal connected to ground; and
a capacitor having a first terminal connected to the drain of the second transistor, and a second terminal connected to ground.
2. The switch unit as claim 1 , wherein a charge of the parasitic capacitor, when the second transistor is turned on, is almost identical to that when the second switch transistor is turned off.
3. A bit-line voltage generator, comprising:
a discharge enhanced bias source; and
a switch unit having a circuit unit and a parasitic capacitor, and connected between the discharged enhanced bias source and a memory array,
wherein the circuit unit makes a charge in the parasitic capacitor, when the switch unit is turned on, almost identical to that when the switch unit is turned off.