Apparatus and method for reduced peak power consumption during common operation of multi-nand flash memory devices
System and method for executing a global memory command in a multi-chip non-volatile memory device having a plurality of non-volatile memories. The global memory command is received at each non-volatile memory concurrently. The memory command is initiated at different times relative to receiving the global memory command for at least two of the plurality of non-volatile memory to mitigate peak power consumption.
1. A method for executing a memory command, the method comprising:
substantially concurrently receiving the memory command at a plurality of non-volatile memories, wherein each of the plurality of non-volatile memories is associated with a respective different identification number; and
delaying execution of the memory command by each of the plurality of non-volatile memories by a respective different amount from a time the memory command is received, wherein each respective different amount is based, at least in part, on the respective different identification number.
2. The method according to claim 1 , wherein each respective different amount is provided by the respective non-volatile memory.
3. The method according to claim 1 , further comprising executing the memory command by each of the plurality of non-volatile memories following a delay of the respective different amount from the time the memory command is received.
4. The method according to claim 3 , wherein the execution of the memory command by one of the plurality of non-volatile memories at least partially overlaps the execution of the memory command by at least another of the plurality of non-volatile memories.
5. The method according to claim 3 , wherein the execution of the memory command by one of the plurality of non-volatile memories occurs after execution of the memory command by at least another of the plurality of non-volatile memories is complete.
6. The method according to claim 3 , further comprising:
substantially concurrently receiving the memory command at an additional non-volatile memory; and
initiating execution of the memory command by the additional non-volatile memory at substantially a same time as the execution of the memory command by one of the plurality of non-volatile memories.
7. The method according to claim 3 , wherein a first delay between the initiation of the execution of the memory command by a first of the plurality of non-volatile memories and a second of the plurality of non-volatile memories is the same as a second delay between the initiation of the execution of the memory command by the second of the plurality of non-volatile memories and a third of the plurality of non-volatile memories.
8. The method according to claim 3 , wherein a first delay between the initiation of the execution of the memory command by a first of the plurality of non-volatile memories and a second of the plurality of non-volatile memories is different than a second delay between the initiation of the execution of the memory command by the second of the plurality of non-volatile memories and a third of the plurality of non-volatile memories.
9. The method according to claim 2 , wherein the respective different identification numbers are each stored within the associated non-volatile memory.
10. A system comprising:
a memory controller configured to issue a memory command;
a bus coupled to the memory controller;
a plurality of non-volatile memories coupled to the bus, wherein the bus is configured to provide the memory command to each of the plurality of non-volatile memories substantially simultaneously, and wherein each of the plurality of non-volatile memories is associated with a respective identification number, each of the non-volatile memories comprises:
a register configured to store the memory command; and
control logic coupled to the register and configured to initiate execution of the memory command following a respective different time delay from receipt of the memory command each respective different time delay is based, at least in part, on the respective different identification number.
11. The system according to claim 10 , wherein each of the non-volatile memories provides the respective different time delay.
12. The system according to claim 10 , further comprising:
a processor coupled to the memory controller; and
an output device coupled to the processor.
13. The system according to claim 10 , wherein the control logic of at least two of the plurality of non-volatile memories are configured to initiate execution of the memory command at different times such that execution of the memory command by one of the plurality of non-volatile memories at least partially overlaps execution of the memory command by one of the two non-volatile memories.
14. The system according to claim 10 , wherein the control logic of at least two of the plurality of non-volatile memories are configured to initiate execution of the memory command at different times such that execution of the memory command by one of the two non-volatile memories occurs after execution of the memory command by the other of the two non-volatile memories is complete.
15. The system according to claim 10 , wherein a first delay between the initiation of the execution of the memory command by a first of the plurality of non-volatile memories and a second of the plurality of non-volatile memories is the same as a second delay between the initiation of the execution of the memory command by the second of the plurality of non-volatile memories and a third of the plurality of non-volatile memories.
16. The system according to claim 10 , wherein a first delay between the initiation of the execution of the memory command by a first of the plurality of non-volatile memories and a second of the plurality of non-volatile memories is different than a second delay between the initiation of the execution of the memory command by the second of the plurality of non-volatile memories and a third of the plurality of non-volatile memories.