MULTI-CHIP PACKAGE STRUCTURE SUITABLE FOR MULTI-PROCESSOR SYSTEM HAVING MEMORY LINK ARCHITECTURE
A multi-chip package structure can include a first package that includes a first circuit board that includes a lower surface including a first circuit pattern thereon and an upper surface, that is opposite the lower surface, and includes an upper pad layer thereon. The multi-chip package structure can further include at least one processor chip that is mounted on the lower surface of the first circuit board. A second package can be mounted on the first package and can include a second circuit board including an upper surface that includes a second circuit pattern thereon and a lower surface, which is opposite the upper surface, which can includes a lower pad layer thereon that is electrically connected to the upper pad layer of the first circuit board. At least one memory chip can be laminated and molded on the upper surface of the second package.
1 . A multi-chip package structure comprising:
a first package including
a first circuit board including a lower surface including a first circuit pattern thereon and an upper surface, opposite the lower surface, including an upper pad layer thereon, and
at least one processor chip mounted on the lower surface of the first circuit board, and
a second package, mounted on the first package, including
a second circuit board including an upper surface including a second circuit pattern thereon and a lower surface, opposite the upper surface, including a lower pad layer thereon electrically connected to the upper pad layer of the first circuit board, and
at least one memory chip laminated and molded on the upper surface of the second package.
2 . The multi-chip package structure of claim 1 , wherein the upper pad layer and the lower pad layer are connected to each other by respective land grid array pads.
3 . The multi-chip package structure of claim 2 , wherein the at least one processor chip is mounted on the lower surface of the first circuit board and is surrounded by contact pads on the lower surface of the first circuit board.
4 . The multi-chip package structure of claim 3 , wherein the at least one processor chip includes a MODEM chip and an application chip.
5 . The multi-chip package structure of claim 4 , wherein the at least one memory chip includes a OneNAND™, a OneDRAM™, and a multi-bank DRAM each having a laminated structure.
6 . A multi-chip package structure comprising:
a first package including
a first circuit board having a lower surface including circuit patterns formed separately and an upper surface, opposite the lower surface, including an upper pad layer thereon and
processor chips mounted on the lower surface of the first circuit board to be connected to the circuit patterns, and
routing lines electrically connecting the processor chips; and a second package including
a second circuit board including an upper surface including a circuit pattern and a lower surface, opposite the upper surface, including a lower pad layer electrically connected to the upper pad layer of the first package, and
at least one memory chip laminated and molded on the upper surface of the second package.
7 . The multi-chip package structure of claim 6 , wherein the upper pad layer and the lower pad layer are connected to each other by land grid array contact.
8 . The multi-chip package structure of claim 7 , wherein the processor chips are mounted on the lower surface of the first circuit board such that each of the processor chips is surrounded by contact pads on the lower surface of the first circuit board.
9 . The multi-chip package structure of claim 6 , wherein the routing lines are in or on the second circuit board.
10 . The multi-chip package structure of claim 9 , wherein the at least one memory chip includes a NAND flash memory, a multi-port semiconductor memory, and a multi-bank DRAM each having a laminated structure.
11 . A multi-chip package structure comprising:
a first package including a first circuit board including a lower surface having a circuit pattern thereon and an upper surface having an upper pad layer thereon, and at least one first processor chip mounted on the lower surface of the first circuit board;
a second package including a second circuit board including a lower surface having a circuit pattern thereon and an upper surface including an upper pad layer thereon, and at least one second processor chip mounted on the lower surface of the second circuit board; and
a third package including
a third circuit board including an upper surface including a circuit pattern and a lower surface including a lower pad layer electrically connected to the upper pad layers of the first and second packages,
at least one memory chip laminated and molded on the upper surface of the third circuit board, and
routing lines electrically connecting the at least one first processor chip and the at least one second processor chip.