Non-volatile FINFET memory device and manufacturing method thereof
View Patent ↗Methods for fabricating an electronic device and electronic devices therefrom are provided. A method includes forming one or more masking layers on a semiconducting surface of a substrate and forming a plurality of dielectric isolation features and a plurality of fin-type projections using the masking layer. The method also includes processing the masking layers and the plurality of fin-type projections to provide an inverted T-shaped cross-section for the plurality of fin-type projections that includes a distal extension portion and a proximal base portion. The method further includes forming a plurality of bottom gate layers on the distal extension portion and forming a plurality of control gate layers on the plurality of dielectric isolation features and the plurality of bottom gate layers.
1. An electronic device, comprising:
a substrate having a semiconducting surface, said semiconducting surface comprising a plurality of fin-type projections with an inverted T -shaped cross-section comprising a proximal base portion and a distal extension portion;
a plurality of dielectric layers disposed on said distal extension portion of said plurality of fin-type projections;
a plurality of dielectric isolation features arranged between said plurality of fin-type projections and extending over sidewall portions of said proximal base portion and having a height being greater than a height of said proximal base portion of said plurality of fin-type projections, wherein a portion of said plurality of dielectric layers substantially fill a region that extends between a portion of a sidewall of said distal extension portion of said plurality of fin-type projections and a sidewall of said plurality of dielectric isolation features and that extends between said height of said proximal base portion and said height of said plurality of dielectric isolation features; and
a plurality of control gate layers disposed on said plurality of dielectric isolation features and other portions of said plurality of dielectric layers.
2. The electronic device of claim 1 , wherein a difference between said height of said dielectric isolation features and said height of said proximal base portion in said plurality of fin-type projections is at least 100 angstroms.
3. The electronic device of claim 1 , wherein a difference between said height of said dielectric isolation features and said height of said proximal base portion in said plurality of fin-type projections is at most 1000 angstroms.
4. The electronic device of claim 1 , wherein an average thickness of said portion of said plurality of dielectric layers is greater than an average thickness of said other portions of said plurality of dielectric layers.
5. The electronic device of claim 1 , wherein said plurality of control gate layers comprise a plurality of coextending lines, and further comprising:
a control element communicatively coupled to said plurality of coextending lines and said plurality of active areas to provide a memory system; and
an electronic device communicatively coupled to said memory system.
6. An integrated circuit, comprising:
a substrate having a silicon surface, said silicon surface comprising a first plurality of fin-type projections with an inverted T-shaped cross-section comprising a proximal base portion and a distal extension portion;
a plurality of dielectric layers disposed on said distal extension portion of said plurality of fin-type projections;
a plurality of dielectric isolation features arranged between said first plurality of fin-type projections and extending over sidewall portions of said proximal base portion and having a height being greater than a height of said proximal base portion of said first plurality of fin-type projections, wherein a portion of said plurality of dielectric layers substantially fill a region that extends between a portion of a sidewall of said distal extension portion of said plurality of fin-type projections and a sidewall of said plurality of dielectric isolation features and that extends between said height of said proximal base portion and said height of said plurality of dielectric isolation features; and
a plurality of control gate layers disposed on said plurality of dielectric isolation features and other portions of said plurality of dielectric layers.
7. The integrated circuit of claim 6 , wherein a difference between said height of said dielectric isolation features and said height of said proximal base portion in said first plurality of fin-type projections is at least 100 angstroms.
8. The integrated circuit of claim 6 , wherein a difference between said height of said dielectric isolation features and said height of said proximal base portion in said first plurality of fin-type projections is at most 1000 angstroms.
9. The integrated circuit of claim 6 , wherein an average thickness of said portion of said plurality of dielectric layers is greater than an average thickness of said other portions of said plurality of dielectric layers.
10. The integrated circuit of claim 6 , further comprising a second plurality of fin-type projections defining a control element portion, wherein said plurality of control gate layers comprises a plurality of lines, and wherein said control element is communicatively coupled to said plurality of lines and said first plurality of fin-type projections to provide a memory system.