Granted Patent B2

US 7,990,201 · App. 12/725,533 · Granted Aug 2, 2011

Abstract

Claims (28)

1. A digital attenuator circuit comprising:

an input node to receive an input signal to be attenuated;

an output node to present an attenuated signal;

a reference loss path between the input node and the output node comprising (i) a plurality of first series transistors and (ii) a plurality of cascaded shunt transistors each connected to a respective one of the plurality of first series transistors, wherein the input signal is varied in response to (a) a first voltage applied to a first biasing node connected to the plurality of first series transistors and (b) a second voltage applied to a second biasing node connected to the plurality of cascaded shunt transistors to improve Voltage Standing Wave Ratio (VSWR), wherein each of said plurality of cascaded shunt transistors receive said second voltage from said second biasing node; and

an attenuation path between the input node and the output node comprising a plurality of second series transistors, wherein the input signal is varied in response to a third voltage applied to a third biasing node connected to the plurality of second series transistors to (i) attenuate the input signal when the digital attenuator circuit is switched from a reference loss state to an attenuation state, (ii) equalize an effective phase length of the reference loss path and an effective phase length of the attenuation path and (iii) provide a constant phase when the digital attenuator circuit is switched between states.

2. The digital attenuator circuit of claim 1 , further comprising:

an interstage inductance element connected to at least one of the input node and the output node to match an output of a previous stage and an input of a next stage.

3. The digital attenuator circuit of claim 2 , wherein the interstage inductance element comprises a high impedance transmission line.

4. The digital attenuator circuit of claim 1 , wherein the reference loss path comprises a shunt resistor connected to each of the plurality of series transistors.

5. The digital attenuator circuit of claim 4 , wherein the reference loss path further comprises a dual gate shunt transistor connected to each of the plurality of series transistors.

6. The digital attenuator circuit of claim 1 , wherein the attenuation path comprises a PI network connected to each of the plurality of series transistors.

7. The digital attenuator circuit of claim 1 , wherein the attenuation path further comprises a plurality of second cascaded shunt transistors each connected to a respective one of the plurality of second series transistors.

8. The digital attenuator circuit of claim 6 , wherein the attenuation path further comprises a dual gate shunt transistor connected to each of the plurality of second series transistors.

9. The digital attenuator circuit of claim 6 , wherein the PI network is configured in accordance with an amount of attenuation to be provided by the digital attenuator circuit.

10. The digital attenuator circuit of claim 1 , wherein said plurality of first series transistors all turn on/off in response to said first biasing node.

11. The digital attenuator circuit of claim 1 , wherein said plurality of cascaded shunt transistors all turn on/off in response to said second biasing node.

12. A method comprising:

providing a digital attenuator circuit on a chip, the digital attenuator circuit comprising:

a reference loss path comprising (i) a plurality of first series transistors and (ii) a plurality of cascaded shunt transistors each connected to a respective one of the plurality of first series transistors, wherein the input signal is varied in response to (a) a first voltage applied to a first biasing node connected to the plurality of first series transistors and (b) a second voltage applied to a second biasing node connected to the plurality of cascaded shunt transistors to improve Voltage Standing Wave Ratio (VSWR), wherein each of said plurality of cascaded shunt transistors receive said second voltage from said second biasing node; and

an attenuation path comprising a plurality of second series transistors, wherein the input signal is varied in response to a third voltage applied to a third biasing node connected to the plurality of second series transistors to (i) attenuate an input signal when the digital attenuator circuit is switched from a reference loss state to an attenuation state, (ii) equalize an effective phase length of the reference loss path and an effective phase length of the attenuation path and (iii) provide a constant phase when the digital attenuator circuit is switched between states.

13. The method of claim 12 , further comprising:

providing a plurality of the digital attenuator circuits on the chip to implement a multi-stage digital attenuator.

14. The method of claim 13 , further comprising:

providing interstage inductance elements for coupling digital attenuator circuits.

15. The method of claim 14 , the interstage inductance elements comprising high impedance transmission lines.

16. The digital attenuator circuit of claim 7 , wherein said input signal is varied in response to a fourth voltage applied to a fourth biasing node connected to the plurality of second cascaded shunt transistors.

17. The method of claim 12 , wherein the attenuation path further comprises a plurality of second cascaded shunt transistors each connected to a respective one of the plurality of second series transistors.

18. The method of claim 17 , wherein said input signal is varied in response to a fourth voltage applied to a fourth biasing node connected to the plurality of second cascaded shunt transistors.

Assignments (7)