Chip identification using top metal layer
View Patent ↗An integrated circuit (IC) structure includes a semiconductor substrate having a plurality of memory bits including IC identification information and a plurality of alternating metal and via layers thereabove. The IC structure includes a bond pad layer formed over a top one of the metal layers. The bond pad layer includes a plurality of pins connected to respective ones of the plurality of memory bits through the metal and via layers, at least one first pad connected to a higher voltage power supply rail and at least one second pad is connected to a lower voltage power supply rail. The bond pad layer has a plurality of circuit segments therein that each connects a respective one of the plurality of pins to either the at least one first pad or the at least one second pad for programming the IC identification information into the memory bit corresponding to that pin.
1. An integrated circuit (IC) structure, comprising:
a semiconductor substrate having a plurality of memory bits and a plurality of alternating metal layers and via layers thereabove, the memory bits including IC identification information; and
a bond pad layer formed over a top one of the metal layers, the bond pad layer including a plurality of pins connected to respective ones of the plurality of memory bits through the metal and via layers, at least one first pad connected to a higher voltage power supply rail and at least one second pad connected to a lower voltage power supply rail,
the bond pad layer having a plurality of circuit segments therein, each of the plurality of circuit segments connecting a respective one of the plurality of pins to either the at least one first pad or the at least one second pad for programming the IC identification information into the memory bit corresponding to that pin.
2. The IC structure of claim 1 , wherein each of the plurality of pins is located between and adjacent to the at least one first pad and the at least one second pad.
3. The IC structure of claim 2 , wherein the at least one first pad includes a plurality of pads arranged along a first line, the at least one second pad includes a plurality of pads arranged along a second line parallel to the first line, and the plurality of pins are arranged in a third line between and parallel to the first and second lines.
4. The IC structure of claim 1 , wherein the bond pad layer is a single layer having pins for programming all of the IC identification information into the memory bits of the semiconductor substrate.
5. The IC structure of claim 1 , wherein the metal layers include circuit paths, and the via layers include vias for connecting circuit paths formed in adjacent metal layers, and each of the plurality of pins is coupled to aligned vias in a plurality of via layers forming a straight vertical path between the pin an intermediate metal layer.
6. The IC structure of claim 1 , wherein the bond pad layer further comprises a human readable pattern indicating a product development number.
7. The IC structure of claim 1 , wherein the bond pad layer further comprises a human readable pattern indicating a copyright notice.
8. The IC structure of claim 1 , wherein the bond pad layer further comprises a human readable pattern indicating a maskwork registration notice.
9. The IC structure of claim 1 , wherein the bond pad layer further comprises a human readable pattern indicating a number of a patent that covers an IC that includes the IC structure.
10. The IC structure of claim 1 ,
wherein the metal layers include circuit paths, and the via layers include vias for connecting circuit paths formed in adjacent metal layers, and
wherein the bond pad layer further includes at least one human readable pattern showing information relating to the IC structure, wherein said human readable pattern is formed directly over the circuit paths.
11. A method, comprising:
providing a semiconductor substrate having a plurality of memory bits and a plurality of alternating metal layers and via layers thereabove, the memory bits including integrated circuit (IC) identification information;
forming a bond pad layer over a top one of the metal layers, the bond pad layer including at least one first pad connected to a higher voltage power supply rail and at least one second pad connected to a lower voltage power supply rail;
forming, in the bond pad layer, a plurality of pins connected to respective ones of the plurality of memory bits through the metal and via layers; and
forming a plurality of circuit segments in the bond pad layer, each of the plurality of circuit segments connecting a respective one of the plurality of pins to either the at least one first pad or the at least one second pad, for programming the IC identification information into the memory bit corresponding to that pin.
12. The method of claim 11 , further comprising using a single mask to form the plurality of pins, the at least one first pad, the at least one second pad, and the plurality of circuit segments, in the bond pad layer.
13. The method of claim 12 , further comprising using the single mask to form a human readable pattern indicating a product development number in the bond pad layer.
14. The method of claim 12 , further comprising using the single mask to form a human readable pattern indicating a copyright notice in the bond pad layer.
15. The method of claim 12 , further comprising using the single mask to form a human readable pattern indicating a maskwork registration notice in the bond pad layer.
16. The method of claim 12 , further comprising using the single mask to form a human readable pattern in the bond pad layer indicating a patent that covers an IC structure.
17. The method of claim 11 , wherein the metal layers include circuit paths, and the via layers include vias for connecting circuit paths formed in adjacent metal layers, the method further comprising the step of forming at least one human readable pattern showing information relating to an IC structure, wherein said human readable pattern is formed directly over the circuit paths.
18. The method of claim 11 , wherein the step of forming the plurality of pins includes forming each of the plurality of pins between and adjacent to the at least one first pad and the at least one second pad.
19. The method of claim 18 , wherein the at least one first pad comprises a plurality of first pads arranged along a first line, and the at least one second pad comprises a plurality of second pads arranged along a second line, and the plurality of pins are arranged in a third line between and adjacent to the first and second lines.
20. The method of claim 11 , further comprising programming all of the IC identification information for the memory bits using a single mask.