Granted Patent B2

US 7,945,744 · App. 12/748,481 · Granted May 17, 2011

Abstract

Claims (23)

1. An interface circuit comprising:

a first output circuit configured to allow an access signal to be input thereto and output the access signal to a storage circuit, the access signal capable of being changed to one logic level or the other logic level for accessing the storage circuit;

a second output circuit configured to output the access signal outputted from the first output circuit; and

a comparison circuit configured to

compare the number of times a logic level of the access signal inputted to the first output circuit is changed and the number of times a logic level of the access signal outputted from the second output circuit is changed, and

output a comparison signal indicating whether or not predetermined access has been performed on the basis of the access signal inputted to the first output circuit,

after at least a part of the access signal is inputted to the first output circuit.

2. The interface circuit according to claim 1 , wherein

the comparison circuit includes:

a first counter configured to count on the basis of a predetermined edge of the access signal inputted to the first output circuit;

a second counter configured to count on the basis of the predetermined edge of the access signal outputted from the second output circuit; and

a comparison signal output circuit configured to

output the comparison signal indicating that the predetermined access has been performed, when an amount of change in count value of the first counter is equal to an amount of change in count value of the second counter, and

output the comparison signal indicating that the predetermined access has not been performed, when the amount of change in count value of the first counter is different from the amount of change in count value of the second counter,

during a time period from a time when at least apart of the access signal is inputted to the first output circuit to a time when a predetermined time has elapsed.

3. The interface circuit according to claim 2 , further comprising

an access signal generation circuit configured to output the access signal to the first output circuit on the basis of the comparison signal indicating that the predetermined access has not been performed.

4. The interface circuit according to claim 2 , wherein

the access signal includes a clock signal with a predetermined cycle; and

the comparison signal output circuit outputs the comparison signal on the basis of the clock signal, after the predetermined time has elapsed since at least a part of the clock signal is inputted to the first output circuit.

5. The interface circuit according to claim 3 , wherein

the access signal includes a clock signal with a predetermined cycle; and

the comparison signal output circuit outputs the comparison signal on the basis of the clock signal, after the predetermined time has elapsed since at least a part of the clock signal is inputted to the first output circuit.

Assignments (7)