IP Library Granted Patent US 7,985,661
Granted Patent B2
US 7,985,661 · App. 12/749,370 · Granted Jul 26, 2011

Semiconductor die singulation method

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Quick Facts
Patent No.
US 7,985,661
App. No.
12/749,370
Granted
Jul 26, 2011
Kind
B2
Abstract

In one embodiment, semiconductor die are singulated from a semiconductor wafer by etching openings completely through the semiconductor wafer.

Claims (30)

1. A method of singulating semiconductor die from a semiconductor wafer comprising:

providing the semiconductor wafer formed from a semiconducting material and having a plurality of semiconductor dies formed on a first surface of the semiconductor wafer and separated from each other by portions of the semiconductor wafer wherein the plurality of semiconductor dies include a dielectric layer covering portions of the plurality of semiconductor dies;

etching a first opening through the dielectric layer and underlying layers to expose a portion of a surface of the semiconductor wafer;

etching through the first opening to extend the first opening from the exposed portion of the surface of the semiconductor wafer into the semiconductor wafer; and

attaching the semiconductor wafer to a carrier tape for supporting the plurality of semiconductor dies after the plurality of semiconductor dies are singulated wherein the attaching step is performed prior to the step of etching through the first opening to extend the first opening and remains attached during the step of etching through the first opening to extend the first opening.

2. The method of claim 1 wherein the step of etching through the first opening includes etching partially through the semiconductor wafer.

3. The method of claim 1 wherein providing the semiconductor wafer includes providing the semiconductor wafer having the dielectric that is formed from a material wherein etching of the dielectric does not etch a metal.

4. The method of claim 1 wherein providing the semiconductor wafer includes providing the semiconductor wafer having the plurality of semiconductor dies having a contact pad on the semiconductor dies and wherein a material of the contact pad is not etched by the etching of the dielectric.

5. The method of claim 1 wherein providing the semiconductor wafer formed from the semiconducting material includes providing the semiconductor wafer formed from silicon.

6. The method of claim 1 further including subsequent to the step of etching through the first opening, using pick-and-place equipment to separate a semiconductor die of the plurality of semiconductor dies from the carrier tape and from other die of the plurality of semiconductor dies.

7. A method of singulating semiconductor die from a semiconductor wafer comprising:

providing the semiconductor wafer having a semiconductor material substrate and having a plurality of semiconductor dies formed on the semiconductor wafer and separated from each other by portions of the semiconductor wafer wherein the plurality of semiconductor dies include a dielectric layer as a top layer;

etching a first opening through the dielectric layer to expose a surface of the semiconductor material substrate; and

using the dielectric layer as a mask and etching through the first opening to extend a depth of the first opening through the portions of the semiconductor material substrate and into the semiconductor material substrate wherein the first opening extends from one surface of the semiconductor material substrate into the semiconductor material substrate thereby creating a space between the plurality of semiconductor dies including attaching the semiconductor wafer to a carrier tape prior to etching through the first opening to extend the depth of the first opening wherein the carrier tape remains attached during the step of etching the first opening.

8. The method of claim 7 wherein using the dielectric layer as the mask and etching through the first opening to extend the depth of the first opening through the portions of the semiconductor material substrate includes etching the opening from a first surface of the semiconductor material substrate through the semiconductor material substrate to a second surface that is opposite to the first surface.

9. The method of claim 7 wherein using the dielectric layer as the mask and etching through the first opening to extend the depth of the first opening through the portions of the semiconductor material substrate includes forming the opening with a width of less than 50 microns.

10. The method of claim 7 wherein using the dielectric layer as the mask and etching through the first opening to extend the depth of the first opening through the portions of the semiconductor material substrate includes etching the opening using an anisotropic etch.

11. The method of claim 7 wherein using the dielectric layer as the mask and etching through the first opening to extend the depth of the first opening through the portions of the semiconductor material substrate includes etching the opening using a combination of isotropic and anisotropic etch.

12. The method of claim 7 further including forming a conductor layer on a second surface of the semiconductor wafer prior to the step of using the dielectric layer as the mask, and wherein the step of using the dielectric layer as the mask includes not etching through the conductor layer that is on the second surface of the semiconductor wafer.

13. The method of claim 7 further including separating a semiconductor die of the plurality of semiconductor dies from other dies of the plurality of semiconductor dies wherein an edge of the first opening is an outside edge of the semiconductor die.

14. A method of singulating semiconductor die from a semiconductor wafer comprising:

providing the semiconductor wafer formed from a semiconducting material and having a plurality of semiconductor dies formed on a first surface of the semiconductor wafer and separated from each other by portions of the semiconductor wafer wherein the plurality of semiconductor dies include a dielectric layer covering portions of the plurality of semiconductor dies;

forming a first opening to expose a portion of a surface of the semiconductor wafer;

etching through the first opening to extend the first opening from the exposed portion of the surface of the semiconductor wafer into the semiconductor wafer; and

attaching the semiconductor wafer to a carrier tape for supporting the plurality of dies after the plurality of dies are singulated wherein the attaching step is performed prior to the step of etching through the first opening to extend the first opening and remains attached during the step of etching through the first opening to extend the first opening.

15. The method of claim 14 wherein the step of etching through the first opening includes etching partially through the semiconductor wafer.

16. The method of claim 14 wherein providing the semiconductor wafer includes providing the semiconductor wafer having the dielectric that is formed from a material wherein etching of the dielectric does not etch a metal.

17. The method of claim 14 wherein providing the semiconductor wafer includes providing the semiconductor wafer having the dielectric that is formed from polyimide.

18. The method of claim 14 wherein providing the semiconductor wafer includes providing the semiconductor wafer having the plurality of semiconductor dies having a contact pad on the semiconductor dies and wherein the dielectric is formed from a material wherein etching of the dielectric does not etch the contact pad.

19. The method of claim 14 further including subsequent to the step of etching through the first opening, using pick-and-place equipment to separate a semiconductor die of the plurality of semiconductor dies from the carrier tape and from other die of the plurality of semiconductor dies.

Assignments (4)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 29, 2010
From: GRIVNA, GORDON M.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 024155/0685 →