Packaged semiconductor device with encapsulant embedding semiconductor chip that includes contact pads
A semiconductor package includes a semiconductor chip, an encapsulant embedding the semiconductor chip, first contact pads on a first main face of the semiconductor package and second contact pads on a second main face of the semiconductor package opposite to the first main face. The diameter d in micrometers of an exposed contact pad area of the second contact pads satisfies d≧(8/25)x+142 μm, wherein x is the pitch of the second contact pads in micrometers.
1. A semiconductor package, comprising:
a semiconductor chip;
an encapsulant embedding the semiconductor chip;
first contact pads on a first main face of the semiconductor package; and
second contact pads on a second main face of the semiconductor package opposite the first main face, wherein a diameter d in micrometers of an exposed contact pad area of the second contact pads satisfies d≧(8/25)x+142 μm, wherein x is a pitch of the second contact pads in micrometers.
2. The semiconductor package of claim 1 , wherein the first contact pads form package terminals arranged to be bonded to a board.
3. The semiconductor package of claim 1 , wherein the second contact pads form package terminals arranged to be bonded to another semiconductor package.
4. The semiconductor package of claim 1 , wherein the exposed contact pad area of the second contact pads is defined by an opening in a solder mask layer overlying a metal layer forming the second contact pads.
5. The semiconductor package of claim 1 , wherein the exposed contact pad area of the second contact pads is defined by lateral dimensions of a metal layer forming the second contact pads.
6. The semiconductor package of claim 1 , wherein the diameter d in micrometers satisfies d≦(8/25)x+172 μm.
7. The semiconductor package of claim 1 , wherein the pitch is x=400 micrometers and the diameter is d≧260 micrometers.
8. The semiconductor package of claim 1 , wherein the pitch is x=500 micrometers and the diameter is d≧300 micrometers.
9. The semiconductor package of claim 1 , wherein the pitch is x=650 micrometers and the diameter is d≧340 micrometers.
10. The semiconductor package of claim 1 , further comprising:
an element having a conductive via, the conductive via extending from the first main face of the semiconductor package to a metal layer forming the second contact pads.
11. The semiconductor package of claim 10 , wherein the element is made of an insulating material.
12. A package-on-package device, comprising:
a first semiconductor package comprising a first semiconductor chip, an encapsulant embedding the first semiconductor chip, first contact pads on a first main face of the first semiconductor package and second contact pads on a second main face of the first semiconductor package opposite the first main face; and
a second semiconductor package comprising a second semiconductor chip, an encapsulant embedding the second semiconductor chip and third contact pads on a first main face of the second semiconductor package,
wherein the first main face of the second semiconductor package faces the second main face of the first semiconductor package and the second contact pads are electrically connected to the third contact pads via solder interconnects, and
wherein a diameter d in micrometers of an exposed contact pad area of the second contact pads satisfies d≧(8/25)x+142 μm, wherein x is a pitch of the second contact pads in micrometers.
13. The package-on-package device of claim 12 , wherein the exposed contact pad area of the second contact pads is defined by an opening in a solder mask layer overlying a metal layer forming the second contact pads.
14. The package-on-package device of claim 12 , wherein the exposed contact pad area of the second contact pads is defined by lateral dimensions of a metal layer forming the second contact pads.
15. The package-on-package device of claim 12 , wherein the diameter d in micrometers satisfies d≦(8/25)x+172 μm.
16. The package-on-package device of claim 12 , wherein the first semiconductor chip is a logic circuit, a power circuit or an optical circuit.
17. The package-on-package device of claim 12 , wherein the second semiconductor chip is a memory chip.
18. The package-on-package device of claim 12 , wherein a spacing between the first main face of the second semiconductor package and the second main face of the first semiconductor package has a dimension that varies by more than 8 micrometers across a lateral extension of the spacing.
19. The package-on-package device of claim 12 , wherein the first main face of the second semiconductor package has a warpage height of at least 8 micrometers across a lateral extension of the first main face.
20. The package-on-package device of claim 12 , wherein the second main face of the first semiconductor package has a warpage height of at least 8 micrometers across a lateral extension of the second main face.