Non-volatile memory device and method for fabricating the same

1. A method for fabricating a non-volatile memory device, the method comprising:

alternately stacking a plurality of interlayer dielectric layers and a plurality of conductive layers over a substrate;

etching the interlayer dielectric layers and the conductive layers to form a trench which exposes a surface of the substrate;

forming a first material layer over an entire surface of a resulting structure in which the trench is formed;

forming a second material layer over the first material layer;

removing portions of the second material layer and the first material layer formed on a bottom of the trench to expose the surface of the substrate;

removing remaining portions of the second material layer; and

filling the trench with a channel layer in which the remaining portions of the second material layer are removed.

2. The method of claim 1 , wherein the first material layer comprises a charge blocking layer, a charge trap layer or a charge storage layer, and a tunnel insulation layer.

3. The method of claim 1 , wherein the first material layer serves as a gate dielectric layer of a select transistor.

4. The method of claim 1 , wherein the second material layer is formed of a material having a high etch selectivity with respect to the first material layer.

5. The method of claim 4 , wherein the second material layer comprises a nitride layer or a carbon layer.

6. The method of claim 4 , wherein the second material layer comprises a polysilicon layer.

7. The method of claim 1 , wherein the second material layer has a thickness ranging from approximately 1 nm to approximately 100 nm.

8. A method for fabricating a non-volatile memory device, the method comprising:

alternately stacking a plurality of interlayer dielectric layers and a plurality of conductive layers over a substrate;

etching the interlayer dielectric layers and the conductive layers to form a trench;

etching the conductive layers exposed by inner walls of the trench by a predetermined thickness to form grooves in the trench;

forming a charge blocking layer, a charge trap layer or a charge storage layer, and a tunnel insulation layer along an entire surface of the trench, including surfaces of the conductive layers exposed by the grooves, wherein the tunnel insulation layer, the charge trap layer or the charge storage layer, and the charge blocking layer are buried in the grooves;

removing portions of the tunnel insulation layer, the charge trap layer or the charge storage layer, and the charge blocking layer formed on a bottom of the trench; and

filling the trench with a channel material.

9. The method of claim 8 , further comprising:

removing the tunnel insulation layer, the charge trap layer or the charge storage layer, and the charge blocking layer formed on the inner walls of the trench from surfaces of the interlayer dielectric layers, so that the tunnel insulation layer, the charge trap layer or the charge storage layer, and the charge blocking layer remain only within the grooves.

10. The method of claim 8 , wherein the etching of the conductive layers by a predetermined thickness to form grooves comprises:

performing an oxidation process to oxidize the conductive layers exposed by the inner walls of the trench to form an oxide layer of a predetermined thickness; and

removing the oxide layer.

11. The method of claim 8 , further comprising forming a passivation layer over the charge blocking layer, the charge trap layer or the charge storage layer, and the tunnel insulation layer formed along the inner walls of the trench.

12. The method of claim 11 , wherein the passivation layer is formed of a material having a high etch selectivity with respect to the tunnel insulation layer.

13. The method of claim 12 , wherein the passivation layer comprises any one of a nitride layer, a carbon layer, and a polysilicon layer.

14. The method of claim 13 , further comprising removing the passivation layer after portions of the passivation layer, the tunnel insulation layer, the charge trap layer or the charge storage layer, and the charge blocking layer formed on the bottom of the trench are removed, when the passivation layer comprises the nitride layer or the carbon layer.

15. The method of claim 13 , further comprising performing a curing process on the passivation layer after the passivation layer, the tunnel insulation layer, the charge trap layer or the charge storage layer, and the charge blocking layer formed on the bottom of the trench are removed, when the passivation layer comprises the polysilicon layer.

16. The method of claim 11 , wherein, in the removing of portions of the tunnel insulation layer, the charge trap layer or the charge storage layer, and the charge blocking layer formed on the bottom of the trench, the passivation layer is removed together, and the passivation layer, the tunnel insulation layer, the charge trap layer or the charge storage layer, and the charge blocking layer formed on the bottom of the trench are etched and removed while leaving the passivation layer, the charge trap layer or the charge storage layer, the charge blocking layer, and the tunnel insulation layer within the grooves.

17. A method for fabricating a vertical channel type non-volatile memory device, the method comprising:

alternately stacking a plurality of interlayer dielectric layers and a plurality of conductive layers over a substrate;

etching the interlayer dielectric layers and the conductive layers to form a trench;

forming a charge blocking layer, a charge trap layer or a charge storage layer, and a tunnel insulation layer along an entire surface of the trench;

forming a passivation layer over the charge blocking layer, the charge trap layer or the charge storage layer, and the tunnel insulation layer formed along the entire surface of the trench; and

removing portions of the passivation layer, the tunnel insulation layer, the charge trap layer or the charge storage layer, and the charge blocking layer formed on a bottom of the trench.

18. The method of claim 17 , wherein the passivation layer comprises polysilicon.

19. The method of claim 17 , further comprising performing a curing process on the passivation layer after the removing of portions of the passivation layer, the tunnel insulation layer, the charge trap layer or the charge storage layer, and the charge blocking layer formed on the bottom of the trench.