IP Library Granted Patent US 8,361,901
Granted Patent B2
US 8,361,901 · App. 12/754,396 · Granted Jan 29, 2013

Die bonding utilizing a patterned adhesion layer

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Quick Facts
Patent No.
US 8,361,901
App. No.
12/754,396
Granted
Jan 29, 2013
Kind
B2
Abstract

An electronic package and method and system for forming the electronic package. The electronic package has a first substrate including a first electronic device and including through-holes extending through an entire thickness of the first substrate. The electronic package has a second substrate bonded to the first substrate, metallizations formed in the through-holes of the first substrate to connect to components of the first electronic device, and a patternable substance disposed between the first substrate and the second substrate and adhering the first substrate and the second substrate together in regions apart from the metallizations. The method and system form through-holes extending through an entire thickness of the first substrate, deposit and pattern an adherable substance on the second substrate in a pattern having openings which expose connections for a second electronic device of the second substrate, align and attach the first substrate and the second substrate together, and form metallizations in the through-holes to connect to the connections for the second electronic device.

Claims (22)

1. A method for forming an electronic package including first and second substrates, comprising:

forming through-holes extending through an entire thickness of the first substrate;

depositing and patterning an adherable substance on the second substrate in a pattern having openings which expose connections to an electronic device of the second substrate;

prior to bonding of the first substrate and the second substrate together, partially curing the adherable substance to a state where the adherable substance is resistant to flow into the through-holes during a subsequent bonding of the first substrate and the second substrate together;

aligning and attaching the first substrate and the second substrate together via the patterned adherable substance without reflow of the adherable substance into the through-holes; and

forming metallizations in the through-holes to connect to said connections for the electronic device.

2. The method of claim 1 , wherein aligning comprises aligning the through-holes with the exposed connections on the second substrate.

3. The method of claim 1 , wherein forming through-holes comprises forming the through-holes in a pattern corresponding to said connections for the second electronic device.

4. The method of claim 3 , wherein forming the through-holes in a pattern comprises:

lithographic patterning and deep ion etching said pattern; or

laser drilling said pattern.

5. The method of claim 1 , wherein attaching comprises adhering the first substrate and the second substrate together with said adherable substance including at least one of an adhesive, an eutectic metal, or a silica based glass.

6. The method of claim 1 , further comprising planarizing said adherable substance prior to said attaching the first substrate and the second substrate together.

7. The method of claim 1 , wherein attaching comprises adhering the first substrate and the second substrate together with a patternable adhesive.

8. The method of claim 7 , wherein attaching comprises adhering the first substrate and the second substrate together with a planarized, patternable adhesive.

9. The method of claim 1 , wherein forming through-holes comprises forming the through-holes in a thinned glass or semiconductor substrate.

10. The method of claim 1 , further comprising forming an insulating film on the walls of said through-holes to insulate a body of the first substrate from said metallizations in the through-holes.

11. A system for forming an electronic package, comprising:

a wafer handler configured to handle a first substrate including through-holes and a second substrate;

a through-hole formation unit configured to form said through-holes in a pattern corresponding to connections for an electronic device of the second substrate;

a metallization unit configured to deposit said metallization into the through-holes to connect to components of the electronic device; and

a wafer processor configured to 1) apply and pattern an adherable substance on the second substrate to produce a pattern in the adherable substance having openings which expose said connections to the second electronic device of the second substrate, 2) align the first and second substrates, and 3) attach the first substrate and the second substrate together.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 10, 2020
From: RESEARCH TRIANGLE INSTITUTE
To: MICROSS ADVANCED INTERCONNECT TECHNOLOGY, LLC
Reel/Frame 052133/0362 →
SECURITY AGREEMENT Recorded Feb 6, 2020
From: MICROSS ADVANCED INTERCONNECT TECHNOLOGY LLC; SILICON TURNKEY SOLUTIONS, INC.
To: ALLY BANK, AS ASSIGNEE
Reel/Frame 051836/0697 →
RELEASE OF SECURITY INTEREST Recorded Feb 6, 2020
From: MIDCAP FINANCIAL TRUST
To: MICROSS ADVANCED INTERCONNECT TECHNOLOGY LLC
Reel/Frame 051834/0394 →
RELEASE OF SECURITY INTEREST Recorded Aug 7, 2017
From: ALLY BANK
To: MICROSS ADVANCED INTERCONNECT TECHNOLOGY LLC
Reel/Frame 043479/0071 →
SECURITY INTEREST Recorded Aug 7, 2017
From: MICROSS ADVANCED INTERCONNECT TECHNOLOGY LLC
To: MIDCAP FINANCIAL TRUST
Reel/Frame 043476/0302 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 18, 2016
From: RESEARCH TRIANGLE INSTITUTE
To: MICROSS ADVANCED INTERCONNECT TECHNOLOGY LLC
Reel/Frame 040387/0745 →
GRANT OF SECURITY INTEREST IN PATENTS Recorded Oct 5, 2016
From: MICROSS ADVANCED INTERCONNECT TECHNOLOGY LLC
To: ALLY BANK
Reel/Frame 040229/0512 →