Granted Patent B2

US 8,212,942 · App. 12/760,405 · Granted Jul 3, 2012

Abstract

Claims (78)

1. A method of controlling a gain in an input digital signal received from a sigma-delta analog-to-digital converter (ΣΔADC) that converts an analog television signal from a tuner to said input digital signal for an analog television receiver, wherein said tuner introduces a DC component to said analog television signal, wherein said input digital signal comprises a video carrier, wherein said video carrier comprising a Luma carrier, and wherein said analog television receiver comprising:

a first cascaded integrator comb (CIC) filter that receives said input digital signal from said ΣΔADC;

a first down-sampler operatively connected to said first CIC filter, said first down-sampler comprising a down sampling factor of two;

a half-band filter operatively connected to said first down-sampler;

a second down-sampler operatively connected to said half-band filter; and

a first adjacent channel interference (ACI) rejection filter operatively connected to said second down-sampler, wherein said first ACI rejection filter comprises an interpolated filter that provides a sharp transition band performance, wherein said interpolated filter comprises a zero-coefficient for alternate taps,

wherein said method comprises:

smoothing, in a de-ripple (De-RPL) filter, an in-band ripple in a filter response from said CIC filter;

removing, in a digital DC offset cancellation block, said DC component introduced by said tuner;

removing, in a programmable notch filter, sinusoid spurs at a plurality of multiple locations in said input digital signal;

receiving, in a gain stage, at least one gain from any of a first automatic gain control block (AGC) and a second AGC block;

detecting, in phase imbalance correction (PIC) circuitry, a correlation between a I and Q components of said video carrier;

removing said correlation;

detecting, in amplitude correction (AIC) circuitry, an imbalance between the magnitudes of said I and Q components;

correcting said imbalance of said I and Q components; and

down-mixing, in a direct digital frequency synthesis (DDFS) circuitry, said Luma carrier of said video carrier to approximately DC.

2. The method of claim 1 , further comprising attenuating, in a second cascaded integrator comb (CIC) filter, a high frequency for said input digital signal based on said down-mixing said Luma carrier of said video carrier to said approximately DC.

3. The method of claim 2 , further comprising:

locking, in a complex phase locked-loop (CPLL) block, a phase of said Luma carrier based on said attenuating, in said second CIC filter, said high frequency for said input digital signal; and

mixing, in said CPLL block, a recovered Luma carrier with an output signal from a delay alignment block to produce a video signal with said Luma carrier exactly at DC,

wherein an output video signal from said CPLL block comprises a baseband video signal with a video carrier exactly at DC, and

wherein said output video signal comprises a vestigial band (VSB) signal.

4. The method of claim 3 , further comprising:

converting, in a vestigial band filter, said VSB signal to a double side band (DSB) signal; and

separating, in a audio and video separation block, an audio signal and a video signal from said double side band (DSB) signal.

5. The method of claim 4 , further comprising comparing, in a moving average filter, a magnitude of said CPLL output video signal with a first threshold value.

6. The method of claim 5 , wherein said gain is increased when said threshold value is larger than said magnitude of said CPLL output video signal, and wherein said gain is decreased when said threshold value is lower than said magnitude of said CPLL output video signal.

7. The method of claim 6 , further comprising:

searching, in a peak search block, a peak of every input digital signal from an output of said moving average filter; and

comparing said peak with a second threshold value.

8. The method of claim 7 , wherein said gain is increased when said threshold value is larger than said peak, and wherein said gain is decreased when said threshold value is lower than said peak.

9. The method of claim 1 , wherein said gain from at least one of said first AGC and said second AGC is received by passing through a multiplexer.

10. A digital front-end architecture to control a gain of an input digital signal for an analog television (TV) receiver, said digital front-end architecture receives said input digital signal from a Sigma-Delta Analog- to-Digital Converter (ΣΔADC), wherein said ΣΔADC converts an analog TV signal from a tuner to said input digital signal, wherein said tuner introduces a DC component, wherein said input digital signal comprises a video carrier, and wherein said video carrier comprises I and Q components, said digital front-end architecture comprising:

a first cascaded integrator comb (CIC) filter that receives said input digital signal;

a first down sampler operatively connected to said CIC filter that receives an output from said CIC filter, wherein said down sampler comprises a sampling factor of two;

a half-band (HB) filter operatively connected to said first down-sampler;

a second down sampler operatively connected to said HB filter comprising a sampling factor of two;

a first adjacent channel interference (ACI) rejection filter operatively connected to said second down sampler, wherein said first ACI filter comprises an interpolation finite impulse response (FIR) filter that provides a sharp transition band performance, wherein said FIR filter comprises a zero-coefficient for alternate taps;

a second ACI filter operatively connected to said first ACI filter, wherein said second ACI filter provides attenuation for a high frequency response of said first ACI filter;

a configurable de-ripple (De-RPL) filter operatively connected to said second ACI filter, wherein said configurable de-ripple (De-RPL) filter smoothens an in-band ripple in response to said CIC filter;

a digital DC offset cancellation (DCO) unit operatively connected to said De-RPL filter, wherein said DCO unit removes said DC component introduced by said tuner;

a programmable notch filter that removes sinusoid spurs at multiple locations in said input digital signal; and

a pair of automatic gain control (AGC) blocks that provide an output to adjust said gain of said input digital signal.

11. The digital front-end architecture of claim 10 , further comprising a gain stage that adjusts said gain of said input digital signal based on an input received from said notch filter and said output of said pair of AGC blocks being multiplexed.

12. The digital front-end architecture of claim 11 , further comprising:

phase imbalance correction (PIC) circuitry operatively connected to said gain stage, wherein said PIC circuitry detects a correlation between the magnitudes of said I and Q components and removes said correlation between the magnitudes of said I and Q components; and

amplitude correction (AIC) circuitry operatively connected to said PIC circuitry that detects an imbalance between the magnitudes of said I and Q components and corrects said imbalance of the gain.

13. The digital front-end architecture of claim 12 , further comprising:

a direct digital frequency synthesis (DDFS) circuitry that down-mixes a Luma carrier of video carrier to approximately DC;

a second cascaded integrator comb (CIC) filter operatively connected to said DDFS circuitry, wherein said second CIC filter attenuates a high frequency of said input digital signal; and

a delay alignment block operatively connected to said DDFS circuitry.

14. The digital front-end architecture of claim 13 , further comprising a complex phase locked loop (CPLL) block operatively connected to said second CIC filter and said delay alignment block, wherein said CPLL block receives an output from said second CIC filter to lock the phase of said Luma carrier based on an output of said CIC filter, wherein said DDFS circuitry and said second CIC filter attenuate the frequency components other than said Luma carrier.

15. The digital front-end architecture of claim 14 , wherein a recovered Luma carrier is mixed with an output from said delay alignment block in said CPLL block to produce a video signal, wherein said video signal comprises a baseband signal with a video carrier exactly at DC, and wherein said video signal comprises a vestigial band (VSB) signal.

16. The digital front-end architecture of claim 15 , further comprising a vestigial band (VSB) block operatively connected to said CPLL block, wherein said VSB block converts said VSB signal to a double side band signal (DSB), and wherein said VSB block comprises a VSB filter that converts said VSB signal to a double side band (DSB) signal.

17. The digital front-end architecture of claim 16 , further comprising:

an audio/video (A/V) separation block operatively connected to said VSB block, wherein said A/V separation block separates an audio signal and a video signal from said DSB signal;

a moving average (MA) filter operatively connected to said A/V separation block, wherein said MA filter compares a magnitude of said CPLL output with a first threshold value, wherein said gain is increased when said threshold value is larger than said magnitude of said CPLL output, and wherein said gain is decreased when said threshold value is lower than said magnitude of said CPLL output; and

a peak search block operatively connected to said MA filter, wherein said peak search block detects a peak of every input digital signal from an output of said moving average filter, and compares said peak with a second threshold value.

18. The digital front-end architecture of claim 17 , wherein said gain is increased when said threshold value is larger than said peak, and wherein said gain is decreased when said threshold value is lower than said peak.

19. A system to control a gain of an input digital signal for analog television (TV) receiver, said system receiving said input digital signal from a Sigma-Delta Analog-to-Digital Converter (ΣΔADC), wherein said ΣΔADC converts an analog TV signal from a tuner to said input digital signal, wherein said tuner introduces a DC component, wherein said input digital signal comprises a video carrier, and wherein said video carrier comprises I and Q components, said system comprising:

a first cascaded integrator comb (CIC) filter that receives said input digital signal from said ΣΔADC;

a first down-sampler operatively connected to said first CIC filter, said first down-sampler comprising a down sampling factor of two;

a half-band filter operatively connected to said first down-sampler;

a second down-sampler operatively connected to said half-band filter;

a first adjacent channel interference (ACI) rejection filter operatively connected to said second down-sampler, wherein said first ACI rejection filter comprises an interpolated filter that provides a sharp transition band performance, wherein said interpolated filter comprises a zero-coefficient for alternate taps;

means for smoothing an in-band ripple in a filter response from said CIC filter;

means for removing said DC component introduced by said tuner;

means for removing sinusoid spurs at a plurality of multiple locations in said input digital signal;

means for receiving at least one gain from at least one of a first automatic gain control block (AGC) and a second AGC block;

means for detecting a correlation between I and Q components of said video carrier and removing said correlation;

means for detecting an imbalance between the magnitudes of said I and Q components and correcting said imbalance of said I and Q components;

means for down-mixing a Luma carrier of said video carrier to approximately DC;

means for converting a vestigial band (VSB) signal to a double side band (DSB) signal;

means for separating an audio signal and a video signal from said double side band (DSB) signal;

means for comparing a magnitude of an output of a complex phase locked-loop (CPLL) block with a first threshold value;

means for searching a peak of every input digital signal from an output of a moving average filter; and

means for comparing said peak with a second threshold value.

20. The system of claim 19 , wherein said gain is increased when said threshold value is larger than said magnitude of said CPLL output video signal, wherein said gain is decreased when said threshold value is lower than said magnitude of said CPLL output video signal, wherein said gain is increased when said threshold value is larger than said peak, and wherein said gain is decreased when said threshold value is lower than said peak.

Assignments (23)