Semiconductor storage device and method of manufacturing same
A semiconductor storage device and method of manufacturing same at a lower cost by without forming a photolithographic resist. Second impurity regions are arranged in such a manner that second impurity regions adjacent along the column direction are joined together. A select gate electrode is arranged into a ring shape so as to surround the second impurity regions, and is electrically connected to a word line. A first control gate electrode is arranged into a ring shape on the outer peripheral side of the select gate electrode, and a second control gate electrode is arranged into a ring shape on the inner peripheral side of the select gate electrode. A pair of first and second bit lines corresponding to every row are placed on the memory cells of the device, a first bit line is electrically connected to one of first impurity regions that are adjacent along the row direction, and a second bit line is electrically connected to the other of the first impurity regions that are adjacent along the row direction.
1. A semiconductor storage device comprising memory cells each having:
first and second impurity regions formed in a substrate on both sides of a channel region;
a select gate electrode formed on the channel region via a gate insulating film; and
first and second control gate electrodes formed into a sidewall shape on both side faces of said select gate electrode and on the surface of the channel region via a gate-isolation insulating film;
wherein said memory cells are arrayed along row and column directions;
said second impurity regions are arranged in such a manner that second impurity regions adjacent along the column direction are joined together, and are electrically connected to a common source line;
said select gate electrode is arranged into a ring shape so as to surround said second impurity regions, and is electrically connected to a word line;
said first control gate electrode is arranged into a ring shape on an outer peripheral side of said select gate electrode;
said second control gate electrode is arranged into a ring shape on an inner peripheral side of said select gate electrode and on an outer peripheral side of said second impurity regions;
said first impurity regions are placed on the outer peripheral side of said first control gate electrode and are arranged in such a manner that first impurity regions adjacent along the column direction are not joined together;
first and second bit lines corresponding to every row are placed on the memory cells;
said first bit line is electrically connected to one of first impurity regions that are adjacent along the row direction sandwiching the second impurity region between them; and
said second bit line is electrically connected to another of said first impurity regions that are adjacent along the row direction sandwiching the second impurity region between them.
2. The device according to claim 1 , wherein said first control gate electrode is electrically connected to ground wiring; and
said second control gate electrode is electrically connected to a wiring whose voltage is controlled.