SEMICONDUCTOR INTEGRATED CIRCUIT AND TESTING METHOD FOR THE SAME
A semiconductor integrated circuit includes: a memory; a logic circuit configured to output an address signal for an address of the memory; and an address control circuit connected with the logic circuit and an address terminal of the memory, and configured to receive a test signal to output one of the address signal from the logic circuit and an output signal having a preset logical value to the address terminal of the memory based on the test signal. The test signal indicates one of a user mode in which a transfer delay fault test is not performed and a test mode in which the transfer delay fault test is performed on a path from the logic circuit to the address terminal of the memory.
1 . A semiconductor integrated circuit comprising:
a memory;
a logic circuit configured to output an address signal for an address of said memory; and
an address control circuit connected with said logic circuit and an address terminal of said memory, and configured to receive a test signal to output one of the address signal from said logic circuit and an output signal having a preset logical value to said address terminal of said memory based on the test signal,
wherein the test signal indicates one of a user mode in which a transfer delay fault test is not performed and a test mode in which the transfer delay fault test is performed on a path from said logic circuit to said address terminal of said memory.
2 . The semiconductor integrated circuit according to claim 1 , wherein said address control circuit comprises:
a scan flip-flop configured to output said output signal;
a NAND gate configured to receive the test signal and said output signal, and output said output signal when the test signal indicates the test mode; and
an AND gate configured to receive the address signal from said logic circuit and said output signal from said NAND gate and output one of the address signal and said output signal to said address terminal of said memory based on said output signal.
3 . The semiconductor integrated circuit according to claim 2 , wherein said address control circuit further comprises:
a multiplexer configured to receive as data inputs, the address signal from said logic circuit and said output signal from said scan flip-flop, receive the test signal as a selection input, output said output signal to said scan flip-flop when the test signal indicates the test mode, and output the address signal to said scan flip-flop when the test signal indicates the user mode.
4 . The semiconductor integrated circuit according to claim 1 , wherein said address control circuit comprises:
a first scan flip-flop configured to output said output signal;
a first multiplexer configured to receive the address signal from said logic circuit and said output signal from said first scan flip-flop as data inputs and a first selection signal a selection input and output one of the address signal and said output signal to said address terminal of said memory in response to the first selection signal;
a second scan flip-flop configured to output a selection signal having a preset logical value; and
an AND gate configured to receive the test signal and the selection signal from said second scan flip-flop, and output the first selection signal to said first multiplexer when the test signal indicates the test mode.
5 . The semiconductor integrated circuit according to claim 4 , wherein said address control circuit further comprises:
a second multiplexer configured to receive the address signal from said logic circuit and said output signal from said first scan flip-flop as data inputs and the test signal as a selection input, and output said output signal to said first scan flip-flop when the test signal indicates the test mode, and output the address signal to said first scan flip-flop when the test signal indicates the user mode.
6 . The semiconductor integrated circuit according to claim 1 , further comprising:
a controller configured to output a test pattern and a BIST control signal for a BIST (Built In Self Test) test on said memory,
wherein said address control circuit receives a BIST test signal and said test pattern from said controller and outputs the test pattern to said address terminal of said memory, when the BIST test signal indicates a BIST test mode in which the BIST test is performed on said memory.
7 . The semiconductor integrated circuit according to claim 6 , further comprising:
an AND gate configured to receive an output signal from said memory and the BIST test signal and supply the output signal from said memory to said controller when the BIST test signal indicates the BIST test mode.
8 . The semiconductor integrated circuit according to claim 6 , wherein said address control circuit comprises:
a first scan flip-flop configured to output a preset signal having a preset logic value;
a first multiplexer configured to receive the preset signal from said first scan flip-flop and the BIST test signal as data inputs and the test signal as a selection input, and output as a selection signal, the preset signal from said first scan flip-flop in the test mode and the BIST test signal in the BIST test mode;
a second scan flip-flop configured to output said output signal based on an input data;
a second multiplexer configured to receive the address signal from said logic circuit and said output signal from said second scan flip-flop as data inputs and the selection signal from said first multiplexer as a selection input, and output to said address terminal of said memory based on the selection signal from said first multiplexer, the address signal from said logic circuit when the normal mode is set and said output signal from said second scan flip-flop when the normal mode is not set,
a third multiplexer configured to output the address signal from said logic circuit when the BIST test mode is not set and the test pattern from said controller when the BIST test mode is set; and
a fourth multiplexer configured to output to said second flip-flop as the input data, an output of said second multiplexer when the test mode is set and an output of said third multiplexer when the test mode is not set.
9 . The semiconductor integrated circuit according to claim 8 , wherein said address control circuit further comprises:
a fifth multiplexer having an output connected with a data input of said first scan flip-flop, and configured to receive the preset signal from said first scan flip-flop and an output signal from said memory, and output the preset signal when the BIST test mode is set and the output signal from said memory when the BIST test mode is set, and
wherein said semiconductor integrated circuit further comprises:
an AND gate configured to output the output signal from said first flip-flop to said controller when the BIST test mode is set.
10 . A test method of a semiconductor integrated circuit, comprising:
receiving an address signal for an address of a memory from a logic circuit, an output signal having a preset logical value and a test signal;
selecting one of the address signal and said output signal based on the test signal; and
outputting the selected signal to an address terminal of said memory,
wherein the test signal indicates one of the user mode in which a transfer delay fault test is not performed and a test mode in which the transfer delay fault test is performed on a path from said logic circuit to said address terminal of said memory, and
wherein the address signal is selected in a user mode and said output signal is selected in a test mode.
11 . The test method according to claim 10 , wherein said selecting comprises:
generating said output signal from a scan flip-flop;
outputting said output signal from a NAND gate when the test signal indicates the test mode; and
selecting the address signal by an AND gate in the user mode; and
selecting said output signal by said AND gate in the test mode.
12 . The test method according to claim 11 , wherein said outputting said output signal from a scan flip-flop comprises:
outputting said output signal from a multiplexer to said scan flip-flop when the test signal indicates the test mode; and
outputting the address signal from said multiplexer to said scan flip-flop when the test signal indicates the user mode.
13 . The test method according to claim 10 , wherein said selecting comprises:
generating said output signal from a first scan flip-flop;
generating a selection signal having a preset logical value from a second scan flip-flop;
outputting the selection signal from an AND gate to a first multiplexer when the test signal indicates the test mode; and
selecting one of the address signal outputted from said logic circuit and said output signal outputted from said first scan flip-flop in response to the selection signal in said first multiplexer.
14 . The test method according to claim 13 , wherein said generating said output signal from a first scan flip-flop further comprises:
receiving said output signal from said first scan flip-flop by a second multiplexer; and
outputting said output signal from the second multiplexer to said first scan flip-flop when the test signal indicates the test mode; and
outputting the address signal from the second multiplexer to said first scan flip-flop when the test signal indicates the user mode.
15 . The test method according to claim 10 , further comprising:
outputting a test pattern and a BIST control signal for a BIST (Built In Self Test) test on said memory from a controller;
wherein said selecting further comprises:
selecting the test pattern, when a BIST test signal indicates a BIST test mode in which the BIST test is performed on said memory.
16 . The test method according to claim 15 , further comprising:
supplying the output signal outputted from said memory to said controller by an AND gate when the BIST test signal indicates the BIST test mode.
17 . The test method according to claim 15 , wherein said selecting comprises:
generating a preset signal having a preset logic value from a first scan flip-flop;
outputting from a first multiplexer as a selection signal, the preset signal in the test mode and the BIST test signal in the BIST test mode;
generating said output signal from a second scan flip-flop based on an input data;
selecting based on the selection signal from said first multiplexer, the address signal outputted from said logic circuit when the normal mode is set and said output signal from said second scan flip-flop when the normal mode is not set;
selecting in a third multiplexer, the address signal outputted from said logic circuit when the BIST test mode is not set and the test pattern outputted from said controller when the BIST test mode is set; and
outputting to said second flip-flop as the input data, an output of said second multiplexer when the test mode is set and an output of said third multiplexer when the test mode is not set.
18 . The test method according to claim 17 , wherein said selecting further comprises:
outputting from a fifth multiplexer to said first scan flip-flop, the preset signal outputted from said first scan flip-flop when the BIST test mode is set and the output signal outputted from said memory when the BIST test mode is set, and
wherein said test method further comprises:
outputting the output signal from said first flip-flop to said controller when the BIST test mode is set.