High performance non-planar semiconductor devices with metal filled inter-fin gaps

1. A non-planar semiconductor transistor device, comprising:

a substrate layer;

a plurality of source and drain electrodes on the substrate layer, with a plurality of corresponding conductive channels extending between corresponding source and drain electrodes; and

a gate stack on the substrate layer, crossing over the plurality of conductive channels, the gate stack extending in a direction perpendicular to the direction in which the conductive channels extend, the gate stack comprising:

a dielectric layer running along the substrate and the plurality of conductive channels and arranged with a substantially uniform layer thickness;

a work-function electrode layer covering the dielectric layer and arranged with a substantially uniform layer thickness;

a metal layer, distinct from the work-function electrode layer, covering the work-function electrode layer and arranged with a substantially uniform height with respect to the substrate such that the metal layer fills a gap between proximate conductive channels of the plurality of conductive channels; and

a barrier layer disposed between the metal layer and the work-function electrode layer, the barrier layer configure to getter an interface layer and reduce a distance between the work-function electrode layer and the conductive channels,

wherein the metal layer of the gate stack is stress-engineered to have an intrinsic state of compressive or tensile stress to provide compressive or tensile stress to the conductive channels.

2. The device of claim 1 , wherein each conductive channel of the plurality of conductive channels comprises a conductive layer and a hard mask layer on top of the conductive layer.

3. The device of claim 1 , wherein the non-planar semiconductor transistor device is a FinFET device.

4. The device of claim 1 , wherein the work-function electrode layer and the metal layer are of a different chemical composition or alloy.

5. The device of claim 1 , wherein the work-function electrode layer conforms to the shape of the top surface of the channels.

6. The device of claim 1 , wherein the metal layer is planarized by a polishing process after deposition.

7. The device of claim 1 , wherein the interface layer is located between the conductive channels and the gate dielectric.

8. The device of claim 1 , wherein the conductive channel is formed of silicon, germanium, SiGe or SiC.

9. The device of claim 1 , wherein the dielectric layer is formed of a semiconductor oxide or high-K dielectric film having a high dielectric constant greater than 3.9.

10. The device of claim 1 , wherein the dielectric layer has a thickness of between approximately 1 nm and approximately 10 nm.

11. The device of claim 1 , wherein the work-function layer is formed of a metal or another conductive material having a desired work function that permits a desired level of electron removal from the conductive channel, wherein the desired work function is within the range of 3.0 eV and 6.0 eV.

12. The device of claim 1 , wherein the work-function layer is formed of TaN, TiN, WN, TiAlN, TaCN, another conductive refractory metal nitride, or an alloy thereof.

13. The device of claim 1 , wherein the metal layer is formed over the work-function layer by sputtering, physical vapor deposition, atomic layer deposition or chemical vapor deposition.

14. The device of claim 1 , wherein the metal layer comprises tungsten, tungsten nitride, or a tungsten aluminum alloy.

15. The device of claim 1 , wherein the thickness of the work-function layer is between approximately 1 nm and 20 nm.

16. A non-planar semiconductor transistor device, comprising:

a substrate layer;

a plurality of source and drain electrodes on the substrate layer, with a plurality of corresponding conductive channels extending between corresponding source and drain electrodes;

a gate stack on the substrate layer, crossing over the plurality of conductive channels, the gate stack extending in a direction perpendicular to the direction in which the conductive channels extend, the gate stack comprising:

a dielectric layer running along the substrate and the plurality of conductive channels and arranged with a substantially uniform layer thickness;

a work-function electrode layer covering the dielectric layer and arranged with a substantially uniform layer thickness; and

a metal layer, distinct from the work-function electrode layer, covering the work-function electrode layer and arranged with a substantially uniform height with respect to the substrate such that the metal layer fills a gap between proximate conductive channels of the plurality of conductive channels, wherein the metal layer is stress-engineered to have an intrinsic state of compressive or tensile stress;

an interface layer located between the conductive channels and the gate dielectric; and

a barrier layer located between the metal layer and the work-function layer that getters the interface layer and reduces the distance of the work-function electrode layer from the conductive channels.

17. The device of claim 16 , wherein each conductive channel of the plurality of conductive channels comprises a conductive layer and a hard mask layer on top of the conductive layer.

18. The device of claim 16 , wherein the non-planar semiconductor transistor device is a FinFET device.

19. The device of claim 16 , wherein the work-function electrode layer and the metal layer are of a different chemical composition or alloy.

20. The device of claim 16 , wherein the work-function electrode layer conforms to the shape of the top surface of the channels.

21. The device of claim 16 , wherein the metal layer is planarized by a polishing process after deposition.

22. The device of claim 16 , wherein the metal layer is formed over the work-function layer by sputtering, physical vapor deposition, atomic layer deposition or chemical vapor deposition.

23. The device of claim 16 , wherein the metal layer comprises tungsten, tungsten nitride, or a tungsten aluminum alloy.