Patent Assignment
Reel/Frame 041804/0940
Assignment of Assignor's Interest
Recorded: 2017-02-24
Pages: 9
Assignor
GLOBALFOUNDRIES INC.
Executed: 2016-12-07
Assignee
AURIGA INNOVATIONS, INC.
303 TERRY FOX DRIVE, SUITE 300, OTTAWA, K2K 3J1, CANADA
Covered Properties
(94)
Freestanding multilayer IC wiring structure
Application:
11/060,802 →
Publication:
US 2005/0151256
Contact Scheme for Finfet Structures with Multiple Fins
Application:
11/448,702 →
Publication:
US 2007/0287256
Device Having a Redundant Structure
Application:
11/746,508 →
Publication:
US 2007/0205515
Structure and Method for Forming a Dielectric Chamber and Electronic Device Including Dielectric Chamber
Application:
11/869,958 →
Publication:
US 2008/0029841
Structure and Method of Creating Entirely Self-Aligned Metallic Contacts
Semiconductor Devices Having Tensile and/or Compressive Strain and Methods of Manufacturing and Design Structure
Final via Structures for Bond Pad-Solder Ball Interconnections
Methods of Fabricating Interconnect Structures Containing Various Capping Materials for Electrical Fuse and Other Related Applications
Design Structure for Interconnect Structure Containing Various Capping Materials for Electrical Fuse and Other Related Applications
Efficient Interconnect Structure for Electrical Fuse Applications
Carrier Mobility Enhanced Channel Devices and Method of Manufacture
Methods of Fabricating a Beol Wiring Structure Containing an on-Chip Inductor and an on-Chip Capacitor
Stabilization of Flatband Voltages and Threshold Voltages in Hafnium Oxide Based Silicon Transistors for Cmos
Application:
12/166,690 →
Publication:
US 2008/0258198
Continuous Metal Semiconductor Alloy via for Interconnects
Body Contacted Hybrid Surface Semiconductor-on-Insulator Devices
A Method of Forming an Interconnect Structure Including a Metallic Interfacial Layer Located at a Bottom via Portion
Multiple Vt Field-Effect Transistor Devices
Through Substrate Vias
Redundant Metal Barrier Structure for Interconnect Applications
Control of Flatband Voltages and Threshold Voltages in High-K Metal Gate Stacks and Structures for Cmos Devices
Finfets and Methods of Making Same
Semiconductor Device Having a Copper Plug
Recessed Contact for Multi-Gate Fet Optimizing Series Resistance
Finfet Spacer Formation by Oriented Implantation
Device Having and Method for Forming Fins with Multiple Widths for an Integrated Circuit
Self-Aligned Composite M-Mox/Dielectric Cap for Cu Interconnect Structures
Nickel-Silicide Formation with Differential Pt Composition
Self-Aligned Contacts for Field Effect Transistor Devices
High Performance Non-Planar Semiconductor Devices with Metal Filled Inter-Fin Gaps
Interconnect Structure for Improved Time Dependent Dielectric Breakdown
Borderless Interconnect Line Structure Self-Aligned to Upper and Lower Level Contact Vias
Simultaneous Formation of Finfet and Mugfet
Formation of Multi-Height Mugfet
Interconnect Structure with Enhanced Reliability
Borderless Contact for Replacement Gate Employing Selective Deposition
Efficient Interconnect Structure for Electrical Fuse Applications
Semiconductor Devices Having Tensile and/or Compressive Strain and Methods of Manufacturing and Design Structure
Methods of Making Fins and Fin Field Effect Transistors (Finfets)
Horizontal Polysilicon-Germanium Heterojunction Bipolar Transistor
Integration of Fin-Based Devices and Etsoi Devices
Patent:
8,236,634 →
Application:
13/050,023 →
Design Structure for Interconnect Structure Containing Various Capping Materials for Electrical Fuse and Other Related Applications
Carrier Mobility Enhanced Channel Devices and Method of Manufacture
Wiring Structure and Method of Forming the Structure
Structure and Method of Creating Entirely Self-Aligned Metallic Contacts
Fin-Last Replacement Metal Gate Finfet
Borderless Contacts in Semiconductor Devices
Finfets and Methods of Making Same
Finfet Device
Multi-Stage Silicidation Process
Finfet with Improved Gate Planarity
Multiple Vt Field-Effect Transistor Devices
Continuous Metal Semiconductor Alloy via for Interconnects
Continuous Metal Semiconductor Alloy via for Interconnects
Nickel-Silicide Formation with Differential Pt Composition
Semiconductor Device Having a Copper Plug
Method of Forming an Interconnect Structure
Body Contacted Hybrid Surface Semiconductor-on-Insulator Devices
Through Substrate Vias
Semiconductor Devices Having Tensile and/or Compressive Strain and Methods of Manufacturing and Design Structure
Redundant Metal Barrier Structure for Interconnect Applications
Integration of Fin-Based Devices and Etsoi Devices
Interconnect Structure Containing Various Capping Materials for Electrical Fuse and Other Related Applications
Control of Flatband Voltages and Threshold Voltages in High-K Metal Gate Stacks and Structures for Cmos Devices
Device Having and Method for Forming Fins with Multiple Widths
Self-Aligned Contacts for Field Effect Transistor Devices
Borderless Contacts in Semiconductor Devices
Borderless Interconnect Line Structure Self-Aligned to Upper and Lower Level Contact Vias
Interconnect Structure Containing a Metallic Interfacial Layer Located at a Bottom of a via Opening
Application:
13/617,060 →
Publication:
US 2013/0001789
Device Having and Method for Forming Fins with Multiple Widths
Application:
13/617,280 →
Publication:
US 2013/0012025
Recessed Contact for Multi-Gate Fet Optimizing Series Resistance
Finfet Spacer Formation by Oriented Implantation
Insulative Cap for Borderless Self-Aligning Contact in Semiconductor Device
Fin Field Effect Transistors Having a Nitride Containing Spacer to Reduce Lateral Growth of Epitaxially Deposited Semiconductor Materials
Insulative Cap for Borderless Self-Aligning Contact in Semiconductor Device
Method of Manufacturing an Enhanced Electromigration Performance Hetero-Junction Bipolar Transistor
Methods of Forming Bulk Finfet Devices by Performing a Recessing Process on Liner Materials to Define Different Fin Heights and Finfet Devices with Such Recessed Liner Materials
Finfet Device Formation
Semiconductor Device Having a Copper Plug
Body Contacted Hybrid Surface Semiconductor-on-Insulator Devices
Interconnect Structure Containing Various Capping Materials for Programmable Electrical Fuses
Interconnect Structure for Improved Time Dependent Dielectric Breakdown
Application:
13/871,337 →
Publication:
US 2013/0234260
Simultaneous Formation of Finfet and Mugfet
Formation of Multi-Height Mugfet
Semiconductor Device Having a Copper Plug
High Performance Non-Planar Semiconductor Devices with Metal Filled Inter-Fin Gaps
Fin-Last Replacement Metal Gate Finfet
Finfet Spacer Formation by Oriented Implantation
Continuous Metal Semiconductor Alloy via for Interconnects
Application:
14/188,028 →
Publication:
US 2014/0167109
Finfet Device
Fin Field Effect Transistors Having a Nitride Containing Spacer to Reduce Lateral Growth of Epitaxially Deposited Semiconductor Materials
Finfet Device Formation
Finfet Devices Having Recessed Liner Materials to Define Different Fin Heights
Semiconductor Devices with Enhanced Electromigration Performance
Interconnect Structure with Enhanced Reliability
Related Assignments
(3)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Sep 3, 2015
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: GLOBALFOUNDRIES U.S. 2 LLC
Reel/Frame 036550/0001 →
Assignment of Assignor's Interest
Oct 5, 2015
From: GLOBALFOUNDRIES U.S. 2 LLC; GLOBALFOUNDRIES U.S. INC.
To: GLOBALFOUNDRIES INC.
Reel/Frame 036779/0001 →
Assignment of Assignor's Interest
Apr 27, 2018
From: AURIGA INNOVATIONS, INC.
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 045650/0571 →