CONTINUOUS METAL SEMICONDUCTOR ALLOY VIA FOR INTERCONNECTS
A contact structure is disclosed in which a continuous metal semiconductor alloy is located within a via contained within a dielectric material. The continuous semiconductor metal alloy is in direct contact with an upper metal line of a first metal level located atop the continuous semiconductor metal alloy and at least a surface of each source and drain diffusion region located beneath the continuous metal semiconductor alloy. The continuous metal semiconductor alloy includes a lower portion that is contained within an upper surface of each source and drain region, and a vertical pillar portion extending upward from the lower portion.
1 . A semiconductor structure comprising:
a substrate comprising a first semiconductor material having a first crystallographic orientation located on portions of a second semiconductor material having a second crystallographic orientation that differs from said first crystallographic orientation;
at last one field effect transistor located on other portions of said second semiconductor material not including said first semiconductor material, wherein said at least one field effect transistor includes at least a gate dielectric, a gate electrode, a source region and a drain region, said gate dielectric has a bottom surface in contact with an upper surface of the second semiconductor material, an upper surface that is coplanar with an upper surface of said first semiconductor material, and vertical edges that are in contact with vertical edges of said first semiconductor material;
a continuous metal semiconductor alloy including a lower portion that is contained within an upper surface of each of said source and drain regions, and a vertical pillar portion extending upwardly from said lower portion; and
a metal line located on an upper surface of said vertical pillar portion of the continuous metal semiconductor alloy.
2 . The semiconductor structure of claim 1 wherein said metal semiconductor alloy is a metal silicide.
3 . The semiconductor structure of claim 1 wherein said metal semiconductor alloy is a metal germanide.
4 . The semiconductor structure of claim 1 wherein vertical pillar portion of the continuous metal semiconductor alloy maintains the same cross section along a vertical axis.
5 . The semiconductor structure of claim 1 wherein the continuous metal semiconductor alloy forms a conductive path between the source region and the metal line.
6 . The semiconductor structure of claim 5 wherein said conductive path is ohmic.
7 . The semiconductor structure of claim 5 wherein said conductive path exhibits variations in electrical potential that are linear.
8 . The semiconductor structure of claim 1 wherein said vertical pillar portion is derived from a single crystal epitaxial semiconductor material.
9 . The semiconductor structure of claim 1 wherein said vertical pillar portion is derived from a semiconductor nanowire.
10 . The semiconductor structure of claim 1 wherein said vertical pillar portion of said continuous metal semiconductor alloy is embedded within a dielectric material.
11 . The semiconductor structure of claim 1 wherein said lower portion and said vertical pillar portion of said continuous metal semiconductor alloy are of unitary construction.
12 . The semiconductor structure of claim 1 wherein no material interface is located between said lower portion and said vertical pillar portion of said continuous metal semiconductor alloy.
13 . The semiconductor structure of claim 1 wherein said lower portion of said continuous metal semiconductor alloy is embedded within said source region and said drain region.
14 . The semiconductor structure of claim 1 wherein said lower portion of said continuous metal semiconductor alloy has a width that is greater than a width of said vertical pillar portion of said continuous metal semiconductor alloy.
15 . The semiconductor structure of claim 1 wherein said at last one field effect transistor comprises spacers located on vertical sidewalls of a patterned gate stack and wherein an edge of said lower portion of said continuous metal semiconductor alloy does not extend beyond an outermost edge of said spacer.
16 . The semiconductor structure of claim 15 wherein an outer vertical edge of said vertical pillar portion of said continuous metal semiconductor alloy is separated from said spacer by a dielectric material.