High performance non-planar semiconductor devices with metal filled inter-fin gaps
View Patent ↗A non-planar semiconductor transistor device includes a substrate layer. Conductive channels extend between corresponding source and drain electrodes. A gate stack extending in a direction perpendicular to the conductive channels crosses over the plurality of conductive channels. The gate stack includes a dielectric layer running along the substrate and the plurality of conductive channels and arranged with a substantially uniform layer thickness, a work-function electrode layer covers the dielectric layer and is arranged with a substantially uniform layer thickness, and a metal layer, distinct from the work-function electrode layer, covers the work-function electrode layer and is arranged with a substantially uniform height with respect to the substrate such that the metal layer fills a gap between proximate conductive channels of the plurality of conductive channels.
1. A CMOS device, comprising:
a substrate layer;
at least one p-type metal oxide semiconductor field-effect transistor; and
at least one n-type metal oxide semiconductor field-effect transistor,
wherein each of the p-type and n-type metal oxide semiconductor field-effect transistors comprise:
a plurality of source and drain electrodes on the substrate layer, with a plurality of corresponding conductive channels extending between corresponding source and drain electrodes; and
a gate stack on the substrate layer, crossing over the plurality of conductive channels, the gate stack extending in a direction perpendicular to the direction in which the conductive channels extend, the gate stack comprising:
a dielectric layer running along the substrate and the plurality of conductive channels and arranged with a substantially uniform layer thickness;
a work-function electrode layer covering the dielectric layer and arranged with a substantially uniform layer thickness;
a metal layer, distinct from the work-function electrode layer, covering the work-function electrode layer and arranged with a substantially uniform height with respect to the substrate such that the metal layer fills a gap between proximate conductive channels of the plurality of conductive channels; and
a barrier layer disposed between the metal layer and the work-function electrode layer, the barrier layer configure to getter an interface layer and reduce a distance between the work-function electrode layer and the conductive channels,
wherein the metal layer of the one or more n-type metal oxide semiconductor field-effect transistors is stress-engineered to have an intrinsic state of compressive or tensile stress to provide compressive or tensile stress to the conductive channels.
2. The device of claim 1 , wherein the metal layer of the one or more n-type metal oxide semiconductor field-effect transistors is formed to have an intrinsic state of tensile stress and the metal layer of the one or more p-type metal oxide semiconductor field-effect transistors is formed to have a compressive state of tensile stress.
3. The device of claim 1 , wherein the metal layer of the one or more n-type metal oxide semiconductor field-effect transistors is formed to have an intrinsic state of tensile or compressive stress and the metal layer of the one or more p-type metal oxide semiconductor field-effect transistors is formed to have the same or opposite state of stress as the metal layer of the one or more n-type metal oxide semiconductor field-effect transistors.
4. The device of claim 1 , wherein the metal layer of the one or more n-type metal oxide semiconductor field-effect transistors and the one or more p-type metal oxide semiconductor field-effect transistors comprises Tungsten or Tungsten Nitride.
5. The device of claim 1 , where in the metal layer of the one or more n-type or p-type metal oxide semiconductor field-effect transistors is formed to have an intrinsic state of tensile or compressive stress and is subsequently de-stressed the on one or more n-type or p-type metal oxide semiconductor field-effect transistors.
6. The device of claim 1 , where in the work-function electrode layer of the one or more n-type metal oxide semiconductor field-effect transistors is formed to have an intrinsic state of tensile or compressive stress and the work-function electrode layer of the one or more p-type metal oxide semiconductor field-effect transistors is formed to have the same or opposite state of stress as the work-function electrode layer of the one or more n-type metal oxide semiconductor field-effect transistors.
7. A FinFET device, comprising:
a substrate layer;
a source and drain electrode on the substrate layer, with a fin-shaped conductive channel extending between the source and drain electrodes;
a dielectric layer running along the substrate and the conductive channel and arranged with a substantially uniform layer thickness;
a work-function electrode layer covering the dielectric layer and arranged with a substantially uniform layer thickness;
a metal layer, distinct from the work-function electrode layer, covering the work-function electrode layer and arranged with a substantially uniform height with respect to the substrate;
an interface layer located between the conductive channel and the dielectric layer; and
a barrier layer located between the metal layer and the work-function electrode layer, the barrier layer configured to getters the interface layer and reduce a distance between the work-function electrode layer and the conductive channel,
wherein the metal layer has an intrinsic state of compressive or tensile stress.
8. The device of claim 7 , wherein the work-function electrode layer and the metal layer are of a different chemical composition or alloy and the work-function electrode layer conforms to the shape of the top surface of the channel.