Nickel-silicide formation with differential Pt composition
View Patent ↗Embodiments of the invention provide a method of forming nickel-silicide. The method may include depositing first and second metal layers over at least one of a gate, a source, and a drain region of a field-effect-transistor (FET) through a physical vapor deposition (PVD) process, wherein the first metal layer is deposited using a first nickel target material containing platinum (Pt), and the second metal layer is deposited on top of the first metal layer using a second nickel target material containing no or less platinum than that in the first nickel target material; and annealing the first and second metal layers covering the FET to form a platinum-containing nickel-silicide layer at a top surface of the gate, source, and drain regions.
1. A field-effect-transistor (FET), comprising:
a gate stack over a channel region;
source and drain regions next to said channel region; and
nickel-silicide formed on top of said source and drain regions,
wherein said nickel-silicide has a top surface and a bottom surface with said bottom surface opposing said top surface and being in contact with said source and drain regions, said nickel-silicide contains platinum which has a platinum concentration level that is higher near said bottom surface than near said top surface of said nickel-silicide and is lower in the middle portion of said nickel-silicide than near said top surface of said nickel-silicide.
2. The FET of claim 1 , further comprising a pair of spacers being formed at sidewalls of said gate stack, wherein said nickel-silicide is formed next to edges of said spacers.
3. The FET of claim 1 , wherein a top surface of said gate stack is silicided to be a platinum-containing nickel-silicide.
4. A field-effect-transistor (FET), comprising:
a gate stack over a channel region;
spacers adjacent to sidewalls of said gate stack;
source and drain regions next to said channel region but separated by said spacers; and
silicide formed at top of said source and drain regions,
wherein said silicide is a platinum-containing nickel-silicide having a concentration level of platinum that is higher near a bottom surface than near a top surface of said silicide and said silicide has a profile of varying platinum concentration level along a depth thereof and wherein said concentration level of platinum in the middle portion of said silicide is lower than that near said bottom and said top surfaces of said silicide.
5. The FET of claim 4 , wherein a top surface of said gate stack is a platinum-containing nickel-silicide.
6. A field-effect-transistor (FET), comprising:
a gate stack over a channel region inside a semiconductor substrate;
spacers adjacent to sidewalls of said gate stack;
source and drain regions, adjacent to said spacers, inside said substrate; and
a silicide layer formed at a top portion of said source and drain regions,
wherein said silicide layer has top surface and a bottom surface and is a platinum-containing nickel-silicide having a concentration level of platinum that is higher near said bottom surface than near said top surface of said silicide layer; said bottom surface is immediately adjacent to rest of said source and drain regions of silicon material; and a platinum concentration level near a middle portion of said silicide layer is lower than that near said top surface.
7. The FET of claim 6 , wherein a platinum concentration level near a middle portion of said silicide layer is lower than that near said top surface.