IP Library Granted Patent US 8,957,479
Granted Patent B2
US 8,957,479 · App. 13/933,356 · Granted Feb 17, 2015

Formation of multi-height MUGFET

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Quick Facts
Patent No.
US 8,957,479
App. No.
13/933,356
Granted
Feb 17, 2015
Kind
B2
Abstract

A method and structure comprise a field effect transistor structure that includes a first rectangular fin structure and a second rectangular fin structure, both positioned on a substrate. The sides of the second rectangular fin structure are parallel to the sides of the first rectangular fin structure. Further, a trench insulator is positioned on the substrate and positioned between a side of the first rectangular fin structure and a side of the second rectangular fin structure. A gate conductor is positioned on the trench insulator, positioned over the sides and the top of the first rectangular fin structure, and positioned over the sides and the top of the second rectangular fin structure. The gate conductor runs perpendicular to the sides of the first rectangular fin structure and the sides of the second rectangular fin structure. Also, a gate insulator is positioned between the gate conductor and the first rectangular fin structure and between the gate conductor and the second rectangular fin structure. The gate conductor is positioned adjacent to a relatively larger portion of the sides of the second rectangular fin structure and is positioned adjacent to a relatively smaller portion of the sides of the first rectangular fin structure.

Claims (42)

1. A field effect transistor structure comprising:

a substrate;

a first rectangular fin structure positioned on said substrate, said first rectangular fin structure having a bottom contacting said substrate, a top opposite said bottom, and sides between said top and said bottom;

a second rectangular fin structure positioned on said substrate, said second rectangular fin structure having a bottom contacting said substrate, a top opposite said bottom, and sides between said top and said bottom, said sides of said second rectangular fin structure being parallel to said sides of said first rectangular fin structure;

a trench insulator positioned on said substrate and positioned between a side of said first rectangular fin structure and a side of said second rectangular fin structure;

a gate conductor positioned on said trench insulator, positioned over said sides and said top of said first rectangular fin structure and positioned over said sides and said top of said second rectangular fin structure, said gate conductor running perpendicular to said sides of said first rectangular fin structure and said sides of said second rectangular fin structure; and

a gate insulator positioned between said gate conductor and said first rectangular fin structure and between said gate conductor and said second rectangular fin structure,

said sides of said first rectangular fin structure comprising a lower portion and an upper portion,

said upper portion of said sides of said first rectangular fin structure being relatively closer to said top of said first rectangular fin structure and said lower portion of said sides of said first rectangular fin structure being relatively farther from said top of said first rectangular fin structure,

said gate conductor being positioned adjacent to said upper portion of said sides of said first rectangular fin structure,

said lower portion of said sides of said first rectangular fin structure being positioned adjacent to said trench insulator,

said gate conductor being positioned adjacent to a relatively larger portion of said sides of said second rectangular fin structure and being positioned adjacent to a relatively smaller portion of said sides of said first rectangular fin structure,

said first rectangular fin structure comprising a central semiconductor portion comprising a channel region, and comprising conductive end portions comprising source and drain regions, and

said second rectangular fin structure comprising a central semiconductor portion comprising a channel region, and comprising conductive end portions comprising source and drain regions.

2. The field effect transistor structure according to claim 1 , further comprising:

a first cap on said top of said first rectangular fin structure, said first cap separating said gate conductor from said first rectangular fin structure; and

a second cap on said top of said second rectangular fin structure, said second cap separating said gate conductor from said first rectangular fin structure.

3. The field effect transistor structure according to claim 1 , said gate insulator separating said gate conductor from said sides and top of first rectangular fin structure, and said gate insulator separating said gate conductor from said sides and top of second rectangular fin structure.

4. The field effect transistor structure according to claim 1 , said first rectangular fin structure and said second rectangular fin structure being one of:

adjacent one another and forming parts of a single transistor device; and

separated from one another on said substrate, and forming parts of different transistor devices on said substrate.

5. The field effect transistor structure according to claim 1 , said first rectangular fin structure and said second rectangular fin structure comprising one of a multiple gate field effect transistor (MUGFET) and a fin-type field effect transistor (FINFET).

6. A field effect transistor structure comprising:

a substrate;

a first rectangular fin structure positioned on said substrate, said first rectangular fin structure having a bottom contacting said substrate, a top opposite said bottom, and sides between said top and said bottom;

a second rectangular fin structure positioned on said substrate, said second rectangular fin structure having a bottom contacting said substrate, a top opposite said bottom, and sides between said top and said bottom, said sides of said second rectangular fin structure being parallel to said sides of said first rectangular fin structure;

a trench insulator positioned on said substrate and positioned between a side of said first rectangular fin structure and a side of said second rectangular fin structure;

a gate conductor positioned on said trench insulator, positioned over said sides and said top of said first rectangular fin structure and positioned over said sides and said top of said second rectangular fin structure, said gate conductor running perpendicular to said sides of said first rectangular fin structure and said sides of said second rectangular fin structure; and

a gate insulator positioned between said gate conductor and said first rectangular fin structure and between said gate conductor and said second rectangular fin structure,

said sides of said first rectangular fin structure comprising a lower portion and an upper portion,

said upper portion of said sides of said first rectangular fin structure being relatively closer to said top of said first rectangular fin structure and said lower portion of said sides of said first rectangular fin structure being relatively farther from said top of said first rectangular fin structure,

said gate conductor being positioned adjacent to said upper portion of said sides of said first rectangular fin structure,

said lower portion of said sides of said first rectangular fin structure being positioned adjacent to said trench insulator,

said gate conductor being positioned adjacent to a relatively larger portion of said sides of said second rectangular fin structure and being positioned adjacent to a relatively smaller portion of said sides of said first rectangular fin structure,

said first rectangular fin structure comprising a central semiconductor portion comprising a channel region, and comprising conductive end portions comprising source and drain regions,

said second rectangular fin structure comprising a central semiconductor portion comprising a channel region, and comprising conductive end portions comprising source and drain regions, and

said first rectangular fin structure and said second rectangular fin structure being adjacent one another and forming parts of a single transistor device.

7. The field effect transistor structure according to claim 6 , further comprising:

a first cap on said top of said first rectangular fin structure, said first cap separating said gate conductor from said first rectangular fin structure; and

a second cap on said top of said second rectangular fin structure, said second cap separating said gate conductor from said first rectangular fin structure.

8. The field effect transistor structure according to claim 6 , said gate insulator separating said gate conductor from said sides and top of first rectangular fin structure, and said gate insulator separating said gate conductor from said sides and top of second rectangular fin structure.

9. The field effect transistor structure according to claim 6 , said first rectangular fin structure and said second rectangular fin structure comprising one of a multiple gate field effect transistor (MUGFET) and a fin-type field effect transistor (FINFET).

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 24, 2017
From: GLOBALFOUNDRIES INC.
To: AURIGA INNOVATIONS, INC.
Reel/Frame 041804/0940 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 5, 2015
From: GLOBALFOUNDRIES U.S. 2 LLC; GLOBALFOUNDRIES U.S. INC.
To: GLOBALFOUNDRIES INC.
Reel/Frame 036779/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2015
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: GLOBALFOUNDRIES U.S. 2 LLC
Reel/Frame 036550/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 15, 2013
From: ANDERSON, BRENT A.; NOWAK, EDWARD J.; RANKIN, JED H.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 031607/0712 →