FinFET with improved gate planarity
View Patent ↗A FinFET with improved gate planarity and method of fabrication is disclosed. The gate is disposed on a pattern of fins prior to removing any unwanted fins. Lithographic techniques or etching techniques or a combination of both may be used to remove the unwanted fins. All or some of the remaining fins may be merged.
1. A method of fabricating a FinFET, comprising:
forming a pattern of fins, wherein each fin comprises a fin hardmask layer disposed thereon;
depositing a gate layer over the pattern of fins;
depositing a gate hardmask layer over the gate layer;
removing a portion of the gate hardmask layer and the gate layer, thereby exposing the pattern of fins;
depositing an etch-resistant layer over a first subset of fins from the pattern of fins;
removing a second subset of the fins from the pattern of fins with an etch; and
merging at least some of the first subset of fins.
2. The method of claim 1 , wherein depositing an etch-resistant layer over a first subset of the fins comprises depositing a layer comprising carbon.
3. The method of claim 1 , wherein depositing an etch-resistant layer over a first subset of the fins comprises depositing a layer comprising photoresist.
4. The method of claim 1 , wherein forming a pattern of fins comprises forming a pattern of fins with a pitch ranging from about 20 nanometers to about 60 nanometers.
5. The method of claim 1 , wherein removing a second subset of the fins further includes a wet etch.
6. The method of claim 1 , wherein removing a second subset of the fins further includes a dry etch.
7. The method of claim 1 , wherein forming a pattern of fins further includes depositing a hardmask comprised of a material selected from the group consisting of:
silicon oxide, silicon nitride, silicon carbide, TiN, TaN, and amorphous carbon.
8. The method of claim 1 , wherein forming a pattern of fins further includes depositing a conformal film of a material selected from the group consisting of:
silicon nitride, silicon carbide, TiN, TaN, and amorphous carbon.
9. A method of fabricating a FinFET, comprising:
forming a pattern of fins, wherein each fin comprises a fin hardmask layer disposed thereon;
removing the fin hardmask layer from a first subset of fins from the pattern of fins;
depositing a gate layer over the pattern of fins;
depositing a gate hardmask layer over the gate layer;
removing a portion of the gate hardmask layer;
removing a portion of the gate layer and the first subset of fins in a single process step, wherein a second subset of fins from the pattern of fins is preserved.
10. The method of claim 9 , further comprising merging at least two fins from the second subset of fins.
11. The method of claim 9 , wherein forming a pattern of fins comprises forming a pattern of fins with a pitch ranging from about 20 nanometers to about 60 nanometers.
12. The method of claim 9 , wherein forming a pattern of fins further includes depositing a hardmask comprised of a material selected from the group consisting of:
silicon oxide, silicon nitride, silicon carbide, TiN, TaN, and amorphous carbon.
13. The method of claim 9 , wherein forming a pattern of fins further includes depositing a conformal film comprised of a material selected from the group consisting of:
silicon nitride, silicon carbide, TiN, TaN, and amorphous carbon.
14. The method of claim 12 , wherein depositing a hardmask of oxide comprises depositing a hardmask layer with a thickness in the range of about 2 nanometers to about 20 nanometers.
15. The method of claim 9 , wherein forming a pattern of fins further includes forming a pattern of fins with a ratio of hardmask thickness to silicon thickness ranging from about 0.05 to about 0.125.