Borderless contacts in semiconductor devices

1. A method, comprising:

depositing a dummy fill material over exposed portions of a substrate and a gate stack disposed on the substrate;

removing portions of the dummy fill material to expose portions of the substrate;

forming a layer of spacer material over the exposed portions of the substrate, the dummy fill material and the gate stack, wherein vertical portions of the spacer material are physically separated from the gate stack by the dummy fill material;

removing horizontal portions of the layer of spacer material to expose portions of the substrate and the dummy fill material;

removing remaining portions of the dummy fill material;

depositing a dielectric layer over the exposed vertical portions of the spacer material, the substrate, and the gate stack, wherein the vertical portions of the spacer material are physically separated from the gate stack by the dielectric layer;

removing portions of the dielectric layer to expose the vertical portions of the spacer material;

removing the vertical portions of the spacer material to expose portions of the substrate and define at least one cavity in the dielectric layer; and

depositing a conductive material in the at least one cavity.

2. The method of claim 1 , wherein the dummy fill material includes an amorphous silicon material.

3. The method of claim 1 , wherein the removing portions of the dummy fill material to expose portions of the substrate and the gate stack includes a photolithographic patterning and etching process.

4. The method of claim 1 , wherein the layer spacer material includes a nitride material.

5. The method of claim 1 , wherein the layer of spacer material includes an oxide material.

6. The method of claim 1 , wherein the removing portions of the layer of spacer material to expose portions of the substrate and the dummy fill material includes an anisotropic etching process.

7. The method of claim 1 , wherein the removing portions of the dielectric layer to expose portions of the spacer material includes a planarization process.

8. The method of claim 1 , wherein the removing exposed portions of the spacer material to expose portions of the substrate and define at least one cavity in the dielectric layer includes exposing at least one active region associated with the gate stack.

9. The method of claim 1 , wherein the depositing a conductive material in the at least one cavity comprises:

depositing a layer of the conductive material in the at least one cavity and over the dielectric layer; and

removing portions of the layer of the conductive material to expose portions of the dielectric layer.

10. A method for forming a field effect transistor device comprising:

depositing a dummy fill material over exposed portions of a substrate, a first gate stack disposed on the substrate, and a second gate stack disposed on the substrate;

removing portions of the dummy fill material to expose portions of the substrate and the second gate stack;

forming a layer of spacer material over the exposed portions of the substrate, the dummy fill material and the second gate stack, wherein vertical portions of the spacer material are physically separated from the first gate stack by the dummy fill material;

removing horizontal portions of the layer of spacer material to expose portions of the substrate and the dummy fill material;

removing remaining portions of the dummy fill material;

depositing a dielectric layer over the exposed vertical portions of the spacer material, the substrate, the first gate stack and the second gate stack, wherein the vertical portions of the spacer material are physically separated from the gate stack by the dielectric layer;

removing portions of the dielectric layer to expose the vertical portions of the spacer material;

removing the vertical portions of the spacer material to expose portions of the substrate and define at least one cavity in the dielectric layer; and

depositing a conductive material in the at least one cavity, the conductive fill material forming a via contacting an active region of the field effect transistor device.

11. The method of claim 10 , wherein the dummy fill material includes an amorphous silicon material.

12. The method of claim 10 , wherein the removing portions of the dummy fill material to expose portions of the substrate and the second gate stack includes a photolithographic patterning and etching process.

13. The method of claim 10 , wherein the layer spacer material includes a nitride material.

14. The method of claim 10 , wherein the layer of spacer material includes an oxide material.

15. The method of claim 10 , wherein the removing portions of the layer of spacer material to expose portions of the substrate and the dummy fill material includes an anisotropic etching process.

16. The method of claim 10 , wherein the removing portions of the dielectric layer to expose portions of the spacer material includes a planarization process.

17. The method of claim 10 , wherein the removing exposed portions of the spacer material to expose portions of the substrate and define at least one cavity in the dielectric layer includes exposing at least one active region associated with the first gate stack.

18. The method of claim 10 , wherein the depositing a conductive material in the at least one cavity comprises:

depositing a layer of the conductive material in the at least one cavity and over the dielectric layer; and

removing portions of the layer of the conductive material to expose portions of the dielectric layer.