Multiple Vt field-effect transistor devices
View Patent ↗Multiple threshold voltage (Vt) field-effect transistor (FET) devices and techniques for the fabrication thereof are provided. In one aspect, a FET device is provided including a source region; a drain region; at least one channel interconnecting the source and drain regions; and a gate, surrounding at least a portion of the channel, configured to have multiple threshold voltages due to the selective placement of at least one band edge metal throughout the gate.
1. A method for fabricating a FET device, comprising the steps of:
patterning a plurality of fins in a silicon-on-insulator (SOI) layer each fin having a first side and a second side opposite the first side;
forming a dielectric layer over each of the fins;
forming a gate that surrounds at least a portion of each of the fins and is separated from the fins by the dielectric layer, the gate being configured to have multiple threshold voltages due to the selective placement of at least one band edge metal throughout the gate such that a portion of the gate adjacent to the first side of each of the fins is configured to have a threshold voltage Vt 1 and a portion of the gate adjacent to the second side of each of the fins is configured to have a threshold voltage Vt 2 , wherein Vt 2 is different from Vt 1 due to the at least one band edge metal being present in the portion of the Rate adjacent to the second side of each of the fins, and wherein the step of forming the gate further comprises the steps of:
depositing a first metal layer over the dielectric layer; and selectively depositing a series of second metal layers over portions of the first metal layer at the second side of each fin; and
forming a source region and a drain region interconnected by the fins.
2. The method of claim 1 , wherein the step of selectively depositing the series of second metal layers, further comprises the steps of:
depositing a gate metal over the portions of the first metal layer at the second side of each of the fins;
depositing the at least one band edge metal over the gate metal; and
interdiffusing the gate metal and the band edge metal throughout the second metal layers.
3. The method of claim 1 , further comprising the steps of:
depositing a third metal layer over the first and second metal layers; and
depositing a polysilicon layer over the third metal layer.
4. The method of claim 1 , wherein Vt 2 is different from Vt 1 due to the at least one band edge metal being present at a greater concentration in the portion of the gate adjacent to the second side of each of the fins.
5. A method for fabricating a FET device comprising the steps of:
patterning a base in a SOI layer having a first side, a second side opposite the first side and a top;
forming a dielectric layer over the base; forming a gate that surrounds at least a portion of the base and is separated from the base by the dielectric layer, the gate being configured to have multiple threshold voltages due to the selective placement of at least one band edge metal throughout the gate such that portions of the gate adjacent to the first and second sides of the base are each configured to have a threshold voltage Vt 1 and a portion of the gate adjacent to the top of the base is configured to have a threshold voltage Vt 2 , wherein Vt 2 is different from Vt 1 due to the at least one band edge metal being present in the portions of the gate adjacent to the first and second sides of the base, and wherein the step of forming the gate further comprises the steps of:
forming a first metal layer and a second metal layer on opposite sides of the base, the first and second metal lavers both comprising the at least one band edge metal; and
forming offset spacers on each side of the base adjacent to the first and second metal lavers; and
forming a source region and a drain region on opposite sides of the gate.
6. The method of claim 5 , wherein the step of forming the first and second metal layers further comprises the steps of:
depositing a metal layer over the dielectric layer, wherein the metal layer comprises the band edge metal; and
selectively removing the metal layer from over a portion of the dielectric layer on top of the base.
7. The method of claim 5 , further comprising the steps of:
removing the offset spacers; and
depositing a top electrode layer over the first and second metal layers and over a portion of the dielectric layer on top of the base.
8. The method of claim 7 , further comprising the step of:
depositing a polysilicon layer over the top electrode layer.
9. The method of claim 5 , further comprising the steps of:
depositing a third metal layer over the offset spacers and over a portion of the dielectric layer on top of the base, wherein the third metal layer comprises a band edge metal that is different from the band edge metal in the first and second metal layers; and
depositing a top electrode layer over the third metal layer.
10. The method of claim 9 , further comprising the step of:
depositing a polysilicon layer over the top electrode layer.
11. The method of claim 5 , wherein Vt 2 is different from Vt 1 due to the at least one band edge metal being present in the portions of the gate adjacent to the first and second sides of the base and absent from the portion of the gate adjacent to the top of the base.