Semiconductor devices having tensile and/or compressive strain and methods of manufacturing and design structure

1. A structure comprising:

gate structures for an NFET and a PFET formed on a top surface of a wafer and having identically formed sidewalls on sides of the NFET and the PFET; and

stress materials in recesses in source and drain regions of the NFET and the PFET,

wherein:

the stress materials in the recesses in the source and drain regions of the NFET and the PFET are raised to a same height above the top surface of the wafer; and

the source and drain regions of the NFET and the PFET have a different amount of stress material due to a different depth of the recesses.

2. The structure of claim 1 , wherein the stress material for the NFET is eSi:C and the stress material for the PFET is eSiGe, wherein the stress material for the NFET is at a depth greater than the stress material for the PFET.

3. The structure of claim 1 , wherein the stress material for the NFET is different than the stress material for the PFET.

4. The structure of claim 3 , wherein the stress material for the NFET is at a depth greater than the stress material for the PFET.

5. The structure of claim 4 , wherein the stress materials are epitaxially grown stress materials.

6. The structure of claim 1 , wherein the recesses of the NFET are deeper than the recesses of the PFET.

7. The structure of claim 1 , wherein the recesses of the PFET are deeper than the recesses of the NFET.

8. The structure of claim 1 , wherein:

the stress material for the PFET is eSiGe; and

the stress material for the NFET is eSi:C.

9. The structure of claim 8 , wherein:

an atomic concentration of germanium in the eSiGe ranges from about 1% to 50%; and

an atomic concentration of carbon in the eSi:C may range from about 0.1% to 10%.

10. The structure of claim 9 , wherein:

the atomic concentration of germanium in the eSiGe ranges about 20% to 40%; and

the atomic concentration of the carbon in the eSi:C ranges from about 1% to 2%.

11. The structure of claim 1 , wherein:

the stress materials are epitaxially grown stress materials comprising eSi:C for the NFET and eSiGe for the PFET;

the stress material for the NFET is at a depth greater than the stress material for the PFET;

the depths of the NFET and the PFET range from about 300 Å to 500 Å;

an atomic concentration of germanium in the eSiGe ranges about 20% to 40%; and

an atomic concentration of the carbon in the eSi:C ranges from about 1% to 2%.

12. The structure of claim 1 , wherein the identically formed sidewalls are tapered sidewall spacers of same material, dimensions, and fabrication.

13. The structure of claim 1 , wherein the stress materials in the recesses in the source and drain regions of the NFET and the PFET are both epitaxially grown above the surface of the wafer.

14. The structure of claim 1 , wherein the stress material in the source and drain region of the NFET is thicker in the depth direction than the source and drain region for the PFET.

15. The structure of claim 14 , wherein:

the stress materials are epitaxially grown stress materials comprising eSi:C in the source and drain region of the NFET and eSiGe in the source and drain region of the PFET; and

an amount the eSiGe is greater than an amount of the eSi:C.

16. The structure of claim 1 , wherein the wafer comprises at least one shallow trench isolation (STI) structure formed between the NFET and PFET, wherein:

the recesses are within the wafer;

the stress materials completely fill the recesses;

the stress materials comprise eSi:C in the source and drain regions of the NFET and eSiGe in the source and drain regions of the PFET;

the stress materials are raised to a same height above the top surface of the wafer and the at least one STI structure such that upper surfaces of the stress materials are co-planar;

bottom surfaces of the stress materials in the source and drain regions of the NFET are at a greater depth in the wafer than bottom surfaces of the stress materials in the source and drain regions of the PFET such that an amount of the eSiC is greater than an amount of the eSi:Ge;

the bottom surfaces of the stress materials in the source and drain regions of the NFET are co-planar; and

the bottom surfaces of the stress materials in the source and drain regions of the PFET are co-planar.

17. A structure comprising:

gate structures for an NFET and a PFET;

identical tapered sidewall spacers of same material, dimensions, and fabrication on sides of the NFET and the PFET; and

stress materials in recesses in source and drain regions of the NFET and the PFET,

wherein:

the source and drain regions of the NFET and the PFET have a different amount of stress material due to a different depth of the recesses in combination with an upper surface of the stress materials of the NFET and the PFET are co-planar and above a top surface of a wafer.

18. The structure of claim 17 , wherein the stress materials in the recesses in the source and drain regions of the NFET and the PFET are both epitaxially grown above the surface of the wafer.

19. The structure of claim 18 , wherein:

the stress materials are epitaxially grown stress materials comprising eSi:C in the source and drain region of the NFET and eSiGe in the source and drain region of the PFET; and

an amount the eSiGe is greater than an amount of the eSi:C.

20. The structure of claim 17 , further comprising a wafer comprising at least one shallow trench isolation (STI) structure formed between the gate structures for the NFET and PFET, wherein:

the recesses are within the wafer;

the stress materials completely fill the recesses;

the stress materials create a tensile strain applied to the NFET and a compressive strain applied to the PFET;

the stress materials comprise eSi:C in the source and drain regions of the NFET and eSiGe in the source and drain regions of the PFET;

the stress materials are raised to a same height above a top surface of the wafer; and

bottom surfaces of the stress materials in the source and drain regions of the NFET are at a greater depth in the wafer than bottom surfaces of the stress materials in the source and drain regions of the PFET such that an amount of the eSiC is greater than an amount of the eSi:Ge.