Control of flatband voltages and threshold voltages in high-k metal gate stacks and structures for CMOS devices
A high-k metal gate stack and structures for CMOS devices and a method for forming the devices. The gate stack includes a high-k dielectric having a high dielectric constant greater than approximately 3.9, a germanium (Ge) material layer interfacing with the high-k dielectric, and a conductive electrode layer disposed above the high-k dielectric or the Ge material layer. The gate stack optimizes a shift of the flatband voltage or the threshold voltage to obtain high performance in p-FET devices.
1. A method of forming a semiconductor structure having an n-type field effect transistor including a first patterned material stack and a p-type field effect transistor including a second patterned material stack, the method comprising:
providing a semiconductor substrate, the first patterned material stack formed over a first region of the substrate and the second patterned material stack formed over a second region of the substrate;
forming an interface preparation layer in the first and second patterned material stacks;
forming a metal nitride layer on the interface preparation layer of only the first patterned material stack;
forming a high-k dielectric layer, having a high dielectric constant greater than approximately 3.9, on the metal nitride layer of the first patterned material stack, and on the interface preparation layer of the second patterned material stack;
forming a Ge material layer on the high-k dielectric of both the first and second patterned material stacks; and
forming a conductive electrode layer above the Ge material layer of both the first and second patterned material stacks.
2. A method of forming a semiconductor structure having an n-type field effect transistor including a first patterned material stack and a p-type field effect transistor including a second patterned material stack, the method comprising:
providing a semiconductor substrate, the first patterned material stack formed over a first region of the substrate and the second patterned material stack formed over a second region of the substrate;
forming a high-k dielectric having a high dielectric constant greater than approximately 3.9;
forming a metal nitride layer in the first patterned material stack interfacing with the high-k dielectric;
forming a Ge material layer only in the second patterned material stack interfacing with the high-k dielectric;
forming a conductive electrode layer above the high-k dielectric, the Ge material layer, or the metal nitride layer; and
forming the metal nitride layer in the second patterned material stack interfacing with the high-k-dielectric.